Please also apply through: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/Tape-Out-Engineer_R-10063230 Role Overview, Responsibilities, and Qualifications The Tape Out Engineer plays a crucial role in the semiconductor design process, serving as the final checkpoint before integrated circuit designs are sent for fabrication. This position is responsible for ensuring that all physical and logical design data meet manufacturing requirements and quality standards, working closely with design, program managers, technologists, and manufacturing teams to resolve issues and optimize outcomes. Key Responsibilities 1. Coordinate and execute the tape out process for semiconductor products, ensuring timely and accurate delivery of design data to manufacturing. 2. Verify design integrity by reviewing database and documentation, and addressing any discrepancies or errors. 3. Work collaboratively with cross-functional teams, including design, technologists, program managers, and process engineering, to resolve technical issues and optimize designs for manufacturability. 4. Ensure all deliverables conform to foundry requirements. 5. Maintain detailed records of tape out procedures, revisions, and outcomes for future reference and process improvement. Qualifications 1. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s preferred). 2. Experience with physical design tools (e.g., Cadence, Synopsys) and semiconductor manufacturing workflows. 3. Excellent attention to detail, problem-solving skills, and ability to work under tight deadlines. 4. Willingness to work with flexible working hours to support critical Tape-outs. Effective communication in English for collaborating across technical teams. This role is ideal for individuals with a passion for precision and innovation, seeking to contribute to the successful launch of leading-edge semiconductor products.

Please also apply on our platform: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/APAC-Foundry-Operations-Senior-Principal-Engineer_R-10062827 Job Description The APAC Foundry Operation team works with foundry partners on technologies which are evaluated and/or subjected to production. The key areas of responsibility of the jobholder are: - Lead the release and transfer of process options at foundries. - Close collaboration with foundries, NXP technology groups, the business lines and various other stakeholders to qualify and release process - Lead and steer the projects towards timely completion to support NXP business needs. - Main decision maker on subjects related to process integration, striking a good balance between the various dynamics in a project; not limiting to technical judgement, resource planning, project schedule, logistics, supplier relationships etc. The requirement fulfilling the job: - Bachelor or MSc in physics, material engineering or electrical engineering. In-depth knowledge of semiconductor physics, process development and manufacturing. - ＞10 years of experience with semiconductor process integration, working in foundries’ production or development teams. - Hands on experience in being a lead; leading teams with responsibilities in development, transfer or production projects. - All rounded knowledge on process integration, product testing, reliability testing, tapeouts, device physics will be needed in the discharge of duties as a project/ integration lead. - Good communication skills. - Pro-active working attitude, creative, pragmatic, enterprising and result driven. - Having the ability to influence and steer a discussion. - Familiar in managing/working with foundries, maximizing leverage from foundries.

***Please upload English resume onto our official platform: https://reurl.cc/qpRoqg Job Description - To work with operation/maintenance to ensure production smoothly. - To assist action confirmations with system monitors. - To work with Engineers for yield improvements from the study of stable plasma cleaning as the leading indicator. Job Qualification: - Understanding of Plasma cleaning principle for wire bonding Integrity Chip die pad/wire type/Lead-post structures - Bachelor‘s or Master‘s student in Material/Science/Electronic Engineering or related - Available to work at least 3 days/week. - Good verbal and written English communication skills - MS Office or Programming skill - Self-motivated, results oriented, willing and eager to learn, proactive attitude

***Please upload English resume onto our official platform: https://reurl.cc/Em0W00 Job Description - To work with IT and Equipment/Production team for MMS (Machine Maintenance Solution) spare part and tool management system build up - To assist Automation project of introducing AMHS (Automatic Material Handling System) for product transportation from wire bond stage to molding stage. Qualifications: - The candidate must be pursuing a Bachelor’s or Master’s degree in Mechanical/Electronic Engineering or related. - Available to work 3 days/ week. - Good verbal and written English communication skills - MS Office, AutoCAD or Programming skill - Self-motivated, results oriented, willing and eager to learn, proactive attitude

Job Description -　Main contact window with business lines (BLs) to deliver a high quality and manufacturable product for IC test production, meeting or exceeding the required time to market or product cost. -　Take lead of new product introduction (NPI) for IC test -　To coordinate with related BLs (business line) and align with wafer/final test factories to prepare the product transfer -　To improve new product introduction procedure to enable smooth product transfer -　To reduce risk and impact to customers and factories, escalation management, e.g. reduce risk and impact by right and timely escalation -　To ensure no gap on test tooling availability Facilitate IC test data review and process for planning forecast, take responsibility on test technical data (and improvement plan) in time and accuracy -　To follow up test improvement projects, hold lots, progress of New Product Introduction, test buy off…etc. -　Process of Test Engineering Notice and Enovia ECO Requirement -　Bachelor degree (or above), Engineering background is preferred. -　Excellent communication skills (English/Mandarin, TOEIC＞600) -　Good logic thinking -　Be familiar with MS Office tool -　1 yrs experience in IC testing or related working experience is preferred

Job Responsibilities - To be the owner for manufacturing test on the released products. - Responsible for test program introduce to mass production - Responsible for NPI (after R-gate released) test data analysis and feedback to BL/PETE if any improvement needed - To be the owner for duplicated test hardware by performing debug and qualification, MSC (Gage R&R) analysis and release report - Responsible for 1st line hold lot disposition, including low yield, QA fail .......etc - To initial and work with related process owners on testing processes, documentation, and best practices - Participate in or drive test automation initiatives when applicable Required Qualifications - 3+ years of experience as a Test Engineer - Solid understanding of software/system testing methodologies - Familiarity with Linux environments and command-line operations - Experience with machine language (e.g., Java, C++) - Experience in system, embedded, hardware, or manufacturing testing - Strong analytical and problem-solving skills - Strong sense of ownership and responsibility for product quality English communication, reading, writing

Role Summary: The NVM Reliability team is responsible for characterizing, modeling, and enabling next-generation Non-Volatile Memory technologies, enabling new product creation company-wide. Job Responsibility: －Interface with foundries and other external suppliers of technology and IP to assess reliability margin to product applications. －Establish qualification requirements for new technology and product introduction. －Perform rigorous statistical analysis of reliability characterization data. －Enable high reliability during volume production by working with product groups to address risk areas. －Support business groups with customer requests for technical information, including reliability characterization results, risks assessments, and consultation on issues. －Communicate study conclusions and recommendations to internal and external teams. Job Qualification: －Bachelor‘s, Masters, or Doctoral degree in Electrical Engineering, Applied Physics, or equivalent, with 10 years of industry experience. －Experienced in data processing and analysis (e.g. Python, JMP, Matlab, Exensio). －Software development experience, such as familiarity with microcontroller software development (C/C++) is desired. －Interest in statistics and solid-state device fundamentals, especially as applied to emerging non-volatile memory technologies like MRAM and RRAM. －Must be curious, proactive, and detail-oriented. －Able to work in a team environment, communicate effectively in English and Mandarin, and solve problems.

***Please apply for this position on NXP official website: https://pse.is/8ms2kr Role Purpose Lead the development and optimization of high-voltage (HV) and BCD device architectures. This role requires a deep understanding of device physics and a data-driven approach to ensure industry-leading performance and reliability for power management solutions. Key Responsibilities － Device Development: Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes. － Physics Analysis: Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI). － Simulation & Modeling: Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles. － Device Verification: Define verification plans and execute statistical analysis using JMP for DOE and WAT data. － Design Integration: Work within Cadence environments for layout review and test structure design. － Cross-functional Collaboration: Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks. Required Qualifications － Experience: Master‘s or Ph.D. in EE, Physics, or related field with 10+ years of semiconductor industry experience. － Technical Expertise: 1. Profound knowledge of Device Architecture and Device Physics. 2. Hands-on experience in 180nm to 55nm BCD process nodes. － Tools: 1. Expertise in TCAD (Sentaurus / Silvaco). 2. Expertise in JMP for statistical data analysis. 3. Proficiency in Cadence (Layout/Virtuoso). Preferred Qualifications (Plus) － Advanced Power Devices: Experience with GaN, SiC, or IGBT development. － Silicon Photonics: Knowledge of Photonics integration and device physics. － Domain Knowledge: 1. Process Integration (PI): Understanding of mask flow and doping profiles. 2. Product Engineering (PE): Experience in CP/FT data correlation and yield enhancement. Competencies － Accountability: Strong ownership of project milestones and outcomes. － Critical Thinking: Ability to identify root causes in complex device failures. － Interpersonal Skills: Effective communication across design and foundry teams. － Data-driven: Committed to objective decision-making through rigorous data analysis.

The key areas of responsibility of the jobholder are: - Collaborate closely with foundries, NXP technology teams, and business lines to qualify and release advanced FinFET processes. - Provide technical leadership in semiconductor device physics, especially in FinFET architecture and behavior. - Interface with internal and external stakeholders on critical development and transfer projects. - Lead and steer projects to meet timelines and business objectives. - Make key decisions on process integration, balancing technical, logistical, and strategic factors. - Support NTI process transfers within foundries and NXP joint ventures Requirements / preferences: - Bachelor‘s or Master‘s degree in Electrical Engineering, Physics, or related field. - Minimum 10 years of experience in semiconductor device engineering, with a strong focus on advanced logic/RF devices. - Proven hands-on experience with HKMG and FinFET technologies in production or development environments. - Deep understanding of semiconductor device physics, especially HKMG and FinFET. - Strong analytical skills in yield enhancement and electrical data analysis. - Fluent in English and Mandarin. - Demonstrated leadership in development, transfer, or ramp-up projects. - Excellent communication and influencing skills. - Proactive, pragmatic, and results-driven mindset. - Experience working with foundries and leveraging external manufacturing capabilities .

1.網站頁面視覺設計：製做Banner、編輯美化、排版設計相關。 2.EDM繪製及排版。 3.品牌包裝設計：規劃品牌系列商品包裝設計 4.協助設計製作平面文宣、海報和DM。 5.協助產品企劃、文案編輯、行銷文件等之規劃 6.其餘主管交辦事項。 **請附上作品集參考**

謙遜有禮、積極進取、具服務熱忱、良好敬業及服務精神。 1.庭園造景施工，植栽栽植移植，美化施工。 2.庭園養護工作，機具操作。例如：喬木修剪、整型樹修剪、澆灌、除草、修剪、整地、施肥、病蟲害防治。 3.工務安排、工作報表填寫與計畫安排。 4.規劃並執行相關園藝教育訓練。(熟悉花草樹木習性尤佳) 5.具備電腦文書及影像處理能力尤佳。 6.工作場域為台中榮民總醫院，有忌諱者勿投履歷。

1.正常供應生產，協助處理產品物料的需求 2.物料保存管理，確保品質 3.主管交辦事項 4.協助主管制定採購流程及相關作業表單，供同仁依循提出採購需求 5.根據物品的庫存量，及過去使用量，決定是否訂購 6.根據需求人員提出之需求做採購 7.正常供應生產，滿足生產對物料的需求 8.物料保存管理，確保品質 9.減少庫存資金積壓，加速現金流動率 10.定期追蹤複查庫存與紀錄是否相輔有無損壞，如不符合找出原因 11.倉庫物品、物料進出管理品，與請購單、發票及其他憑證是否相符 12.將進貨紀錄在帳冊或卡片

您對補習教育事業感興趣嗎？ 您是否喜愛孩子並充滿耐心與關懷呢？ 歡迎加入葛洛莉的大家庭，與我們共同學習與成長！ ＜＜有經驗者另有加給＞＞ 《工作內容》 ◆課程諮詢及招生活動規劃 ◆校務活動規劃與執行 ◆學生安全管理 ◆維持教學品質 ◆客戶經營 ◆其它校務行政工作 ◆ 獎金類 1.每月業績獎金 2.每季績效獎金 3.年度目標獎金 4.活動目標獎金 ◆ 福利類 1.年終獎金 2.工作考核獎金 3.年資久任獎金 4.每年證照獎金 5.首年簽約獎金 5.四節獎金(春節, 端午, 中秋, 教師節 ) 6.生日禮金、結婚禮金、生育禮金 7.年資特休、婚假、產檢假、產假 8.提供外縣市全職行政人員15個月免租金之住宿 ◆ 保險類 1.勞保、健保 2.勞退6％提撥金 3.員工團體保險 ◆ 休閒類 1.員工旅遊 2.員工健行、聚餐 3.員工尾牙/春酒 ◆ 制度類 1.提供員工完整的教育訓練 2.順暢的升遷管道與加薪 工作時間：一/二/四:14:00~22:00(排班) 三/五:12:00~22:00(排班) 六:9:00~17:00 依上述時間排班，每週5天，每週工時合計40小時，週休二日。 工作地點：桃園地區分校 學校網址：http://www.glo.com.tw

您對補習教育事業感興趣嗎？ 您是否喜愛孩子並充滿耐心與關懷呢？ 歡迎加入葛洛莉的大家庭，與我們共同學習與成長！ ＜＜有經驗者另有加給＞＞ 《工作內容》 ◆課程諮詢及招生活動規劃 ◆校務活動規劃與執行 ◆學生安全管理 ◆維持教學品質 ◆客戶經營 ◆其它校務行政工作 ◆ 獎金類 1.每月業績獎金 2.每季績效獎金 3.年度目標獎金 4.活動目標獎金 ◆ 福利類 1.年終獎金 2.工作考核獎金 3.年資久任獎金 4.每年證照獎金 5.首年簽約獎金 5.四節獎金(春節, 端午, 中秋, 教師節 ) 6.生日禮金、結婚禮金、生育禮金 7.年資特休、婚假、產檢假、產假 8.提供外縣市全職行政人員15個月免租金之住宿 ◆ 保險類 1.勞保、健保 2.勞退6％提撥金 3.員工團體保險 ◆ 休閒類 1.員工旅遊 2.員工健行、聚餐 3.員工尾牙/春酒 ◆ 制度類 1.提供員工完整的教育訓練 2.順暢的升遷管道與加薪 工作時間：一/二/四:14:00~22:00(排班) 三/五:12:00~22:00(排班) 六:9:00~17:00 依上述時間排班，每週5天，每週工時合計40小時，週休二日 工作地點：中壢地區分校 學校網址：http://www.glo.com.tw

1. 督導製程生產狀況及品質正常。 2. 撰寫製程異常狀況報告。 3. 研究與執行製程及設備改善方案。 4. 巡查轄區作業環境，督導人員作業安全。 5. 督導轄區內承攬商人員遵守各項安全規定，並依標準作業程序執行作業。 6. 推動並執行工廠PSM（製程安全管理）。 7. 督導轄區內工安及環保要求，並改善相關缺失。

【職務說明】 1.兒童美語教學 2.教學活動規劃與課後輔導 3.電話輔導測驗及作業批改 4.親師聯絡及相關事項 5.其他相關教務工作 【人格特質】 1.對兒幼教育有熱忱，充滿愛心及耐性 2.細心且樂於與人相處及溝通 【福利津貼】 *紅利津貼 *依年資計薪，有議薪空間 *員工聚餐 *員工旅遊 *健檢 *專業新師訓/主管訓

1.拜訪固定或非固定地區醫院、診所、藥局客戶，以開發或維護客戶關係。 2.銷售及推廣公司產品，例如營養保健產品等。 3.教育及示範產品使用方式。 4.協助客戶使用產品。 5.提供新客戶相關之行銷或經營輔導。

1.文書資料建檔報告 2.接聽廠商來電 3.估價單/請款單製做 4.其他主管交辦事項 5.消防審勘掛領件 6.消防平面圖繪製cad檔

1.車床操作機器設備之保養與維護 2.負責產品測試與量測，協助改善製程品質與追蹤 3.協助管理生產流程、控制工件尺寸及品質、加工現場安全監管 ***需熟星辰B12、L12機台，有經驗可詳談***