1.負責門禁管制、車輛出入指揮、巡邏、防竊作業及竊盜處理工作等安全維護工作 2.針對特定處所進行監視，維持公共安全，減少火災、竊盜或其他危險 3.控制照明、取暖、空氣調節及通風等設備 4.監督及參與建築及設備之清潔、修理及維護

1.負責門禁管制、車輛出入指揮、案場巡邏、防竊作業及竊盜處理工作等安全維護工作 2.收發文件 3.針對特定處所進行監視，維持公共安全，減少火災、竊盜或其他危險 4.控制照明、取暖、空氣調節及通風等設備 5.現場安全維護管理、保障客戶生命和財產安全

人員車輛管制 及平交道安全維護 需具備國民中學以上學歷(證明文件) 06-22 依值勤位置不同 每日值勤8小時

梧棲沙鹿地區醫院保全 工作內容 1.引導客人至指定位置 2.前置引現場讓醫護動線無障礙 3.協助上下車病人 4.交通指揮

1.高階主管日常行程掌握、國內外差旅及會議安排。 2.大型會議與會主管通知，追蹤處理決議事項。 3.重要餐敘舉辦。 4.文件呈送整理，並能追踨進度掌握簽核時效。 5.重要外賓來訪接待及其他例行性秘書工作。 6.主管交辦事項。

1.協助主管及各項會議之日文口譯、現場溝通翻譯。 2.負責日文文件、信件及相關資料翻譯與彙整。 3.協助處理日文相關業務聯繫及跨部門溝通。 4.安排主管行程、會議及相關行政作業。 5.協助部門行政事務及主管交辦事項。

1.櫃台接待、電話接聽 2.行政文件檔案整理 3.環境基本維持

1.CNC機台取放料作業 2.報表填寫 早班：08:00~17:00 中午休息12:00~13:00 中午公司供餐 見紅休 **公司享勞健保、新制勞退金、特休假、

門市 *對品牌專櫃門市銷售具高度熱忱. *活潑開朗，喜歡與人群接觸， *負責介紹商品，陳列商品，清潔櫥窗，維持營業場所的整潔與美觀， 店長: 配合公司政策，領導員工落實公司制度 ， 計劃和監督人員相關的訓練， 廣告活動規劃，協調及促銷宣傳，

1. 定期維護、保養生產設備機台，並進行故障排除、異常分析與追蹤處理。 2. 規劃生產設備之操作順序，以便正確使用設備，進而提升生產效率。 3. 進行設備改造、升級或開發，以便提升設備的生產力。 4. 規劃有關設備空間的安排，並說明規劃的功效。 5. 評估新設備之整體效能，並將通過評估的新設備導入產線。 6. 設備相關SOP規範制定。 7. 配合度高。

1.收銀機結帳 2.幫客人夾取麵包 3.其他主管交辦事項 ※請撥櫃上電話預約面試0976-068232

1.進駐客人登記資料、房間分配 2.將顧客的行李送進房間 3.告知顧客飯店相關的規定以及週遭環境的資訊 4.將顧客的問題告知相關部門，讓顧客問題能夠圓滿解決 5.協助顧客使用飯店各項設施以及活動 6.結束住宿時，替客戶做退房的動作 7.協助處理主管交代事務

1.保養作業及備品倉儲作業 2.負責工作區域清潔工作 3.負責日常清潔保養工作 4.責任區域內設備故障通報 5.維護公共區域環境清潔與保養維護 6.完成主管交辦事務 7.有經驗者佳

Please also apply through: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/Tape-Out-Engineer_R-10063230 Role Overview, Responsibilities, and Qualifications The Tape Out Engineer plays a crucial role in the semiconductor design process, serving as the final checkpoint before integrated circuit designs are sent for fabrication. This position is responsible for ensuring that all physical and logical design data meet manufacturing requirements and quality standards, working closely with design, program managers, technologists, and manufacturing teams to resolve issues and optimize outcomes. Key Responsibilities 1. Coordinate and execute the tape out process for semiconductor products, ensuring timely and accurate delivery of design data to manufacturing. 2. Verify design integrity by reviewing database and documentation, and addressing any discrepancies or errors. 3. Work collaboratively with cross-functional teams, including design, technologists, program managers, and process engineering, to resolve technical issues and optimize designs for manufacturability. 4. Ensure all deliverables conform to foundry requirements. 5. Maintain detailed records of tape out procedures, revisions, and outcomes for future reference and process improvement. Qualifications 1. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s preferred). 2. Experience with physical design tools (e.g., Cadence, Synopsys) and semiconductor manufacturing workflows. 3. Excellent attention to detail, problem-solving skills, and ability to work under tight deadlines. 4. Willingness to work with flexible working hours to support critical Tape-outs. Effective communication in English for collaborating across technical teams. This role is ideal for individuals with a passion for precision and innovation, seeking to contribute to the successful launch of leading-edge semiconductor products.

Please also apply on our platform: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/APAC-Foundry-Operations-Senior-Principal-Engineer_R-10062827 Job Description The APAC Foundry Operation team works with foundry partners on technologies which are evaluated and/or subjected to production. The key areas of responsibility of the jobholder are: - Lead the release and transfer of process options at foundries. - Close collaboration with foundries, NXP technology groups, the business lines and various other stakeholders to qualify and release process - Lead and steer the projects towards timely completion to support NXP business needs. - Main decision maker on subjects related to process integration, striking a good balance between the various dynamics in a project; not limiting to technical judgement, resource planning, project schedule, logistics, supplier relationships etc. The requirement fulfilling the job: - Bachelor or MSc in physics, material engineering or electrical engineering. In-depth knowledge of semiconductor physics, process development and manufacturing. - ＞10 years of experience with semiconductor process integration, working in foundries’ production or development teams. - Hands on experience in being a lead; leading teams with responsibilities in development, transfer or production projects. - All rounded knowledge on process integration, product testing, reliability testing, tapeouts, device physics will be needed in the discharge of duties as a project/ integration lead. - Good communication skills. - Pro-active working attitude, creative, pragmatic, enterprising and result driven. - Having the ability to influence and steer a discussion. - Familiar in managing/working with foundries, maximizing leverage from foundries.

Job Responsibilities - To be the owner for manufacturing test on the released products. - Responsible for test program introduce to mass production - Responsible for NPI (after R-gate released) test data analysis and feedback to BL/PETE if any improvement needed - To be the owner for duplicated test hardware by performing debug and qualification, MSC (Gage R&R) analysis and release report - Responsible for 1st line hold lot disposition, including low yield, QA fail .......etc - To initial and work with related process owners on testing processes, documentation, and best practices - Participate in or drive test automation initiatives when applicable Required Qualifications - 3+ years of experience as a Test Engineer - Solid understanding of software/system testing methodologies - Familiarity with Linux environments and command-line operations - Experience with machine language (e.g., Java, C++) - Experience in system, embedded, hardware, or manufacturing testing - Strong analytical and problem-solving skills - Strong sense of ownership and responsibility for product quality English communication, reading, writing

Role Summary: The NVM Reliability team is responsible for characterizing, modeling, and enabling next-generation Non-Volatile Memory technologies, enabling new product creation company-wide. Job Responsibility: －Interface with foundries and other external suppliers of technology and IP to assess reliability margin to product applications. －Establish qualification requirements for new technology and product introduction. －Perform rigorous statistical analysis of reliability characterization data. －Enable high reliability during volume production by working with product groups to address risk areas. －Support business groups with customer requests for technical information, including reliability characterization results, risks assessments, and consultation on issues. －Communicate study conclusions and recommendations to internal and external teams. Job Qualification: －Bachelor‘s, Masters, or Doctoral degree in Electrical Engineering, Applied Physics, or equivalent, with 10 years of industry experience. －Experienced in data processing and analysis (e.g. Python, JMP, Matlab, Exensio). －Software development experience, such as familiarity with microcontroller software development (C/C++) is desired. －Interest in statistics and solid-state device fundamentals, especially as applied to emerging non-volatile memory technologies like MRAM and RRAM. －Must be curious, proactive, and detail-oriented. －Able to work in a team environment, communicate effectively in English and Mandarin, and solve problems.

***Please apply for this position on NXP official website: https://pse.is/8ms2kr Role Purpose Lead the development and optimization of high-voltage (HV) and BCD device architectures. This role requires a deep understanding of device physics and a data-driven approach to ensure industry-leading performance and reliability for power management solutions. Key Responsibilities － Device Development: Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes. － Physics Analysis: Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI). － Simulation & Modeling: Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles. － Device Verification: Define verification plans and execute statistical analysis using JMP for DOE and WAT data. － Design Integration: Work within Cadence environments for layout review and test structure design. － Cross-functional Collaboration: Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks. Required Qualifications － Experience: Master‘s or Ph.D. in EE, Physics, or related field with 10+ years of semiconductor industry experience. － Technical Expertise: 1. Profound knowledge of Device Architecture and Device Physics. 2. Hands-on experience in 180nm to 55nm BCD process nodes. － Tools: 1. Expertise in TCAD (Sentaurus / Silvaco). 2. Expertise in JMP for statistical data analysis. 3. Proficiency in Cadence (Layout/Virtuoso). Preferred Qualifications (Plus) － Advanced Power Devices: Experience with GaN, SiC, or IGBT development. － Silicon Photonics: Knowledge of Photonics integration and device physics. － Domain Knowledge: 1. Process Integration (PI): Understanding of mask flow and doping profiles. 2. Product Engineering (PE): Experience in CP/FT data correlation and yield enhancement. Competencies － Accountability: Strong ownership of project milestones and outcomes. － Critical Thinking: Ability to identify root causes in complex device failures. － Interpersonal Skills: Effective communication across design and foundry teams. － Data-driven: Committed to objective decision-making through rigorous data analysis.

The key areas of responsibility of the jobholder are: - Collaborate closely with foundries, NXP technology teams, and business lines to qualify and release advanced FinFET processes. - Provide technical leadership in semiconductor device physics, especially in FinFET architecture and behavior. - Interface with internal and external stakeholders on critical development and transfer projects. - Lead and steer projects to meet timelines and business objectives. - Make key decisions on process integration, balancing technical, logistical, and strategic factors. - Support NTI process transfers within foundries and NXP joint ventures Requirements / preferences: - Bachelor‘s or Master‘s degree in Electrical Engineering, Physics, or related field. - Minimum 10 years of experience in semiconductor device engineering, with a strong focus on advanced logic/RF devices. - Proven hands-on experience with HKMG and FinFET technologies in production or development environments. - Deep understanding of semiconductor device physics, especially HKMG and FinFET. - Strong analytical skills in yield enhancement and electrical data analysis. - Fluent in English and Mandarin. - Demonstrated leadership in development, transfer, or ramp-up projects. - Excellent communication and influencing skills. - Proactive, pragmatic, and results-driven mindset. - Experience working with foundries and leveraging external manufacturing capabilities .

- Data analysis to ensure handler work on baseline. Ex. MCBA, index time, temperature control and HW interface maintenance 資料分析確保機台運作在基準條件, 包含作動不順, 作動時間, 溫度控制, 及機台介面維護 - SOP, OCAP, PM document creation. 建立標準化流程,異常處理文件,及保養維護文件 - Responsible for the performance of handler. 負責機台性能及相關報告 - Handle the improvement project on handler. 持續進行機台的改善計畫 - Management recipes of handler and spare parts 機台參數管理及備品管理 - Provide technology and operation training to shift assistant engineer and operators in manufacture lines to support production smoothly. 訓練助理工程師與作業員以利生產線順利運作 - Co-work with worldwide handler team for evaluation/improvement 與其他機台團隊跨國合作, 導入評估, 問題改善