CSR專區

1. 負責儀電設備檢修、安裝、校正、保養及操作等工作。 2. 維持廠內儀電設備正常運作。 3. 線路故障排除修護。 4. 拉線及配電管工作。 5. 完成主管交付事項。

1. 負責儀電設備檢修、安裝、校正、保養及操作等工作。 2. 維持廠內儀電設備正常運作。 3. 線路故障排除修護。 4. 拉線及配電管工作。 5. 完成主管交付事項。

歡迎喜歡挑戰自我的你加入~ 1.簡單電腦系統操作 2.協助直播進行 3.幕後其他事項 4.完成主管交代事項 無經驗可，詳細工作內容可透過面試詳談

1.工地現場監工、工程數量估算、上下游廠商連絡等事宜 、幫助震動機司機打設鋼板樁工程 2.在工地現場負責工程、人員、資源的督導、調動、協商、審核、各項數量計算及檢核等工作 3.工地一切相關工作事項 4.完成主管交待事項 5.有證照無證照皆可，但需有相關經驗佳，無經驗也可 6.需有營造業職安卡 7.工地工作為戶外勞動 工作地點:雲嘉南以北 8.設有三節獎金、年終獎金

1.工地現場打設、拔除鋼板樁作業，協助吊料上板、下板車 2.板樁數量估算、上下游廠商連絡等事宜 3.需有重機械操作挖掘機證照，需有相關工地經驗 4.需有營造業職安卡 5.工地狀況回報及處理 6.完成主管交待事項 7.工地工作為戶外勞動 工作地點:雲嘉南以北 8.設有三節獎金、年終獎金

協助廚師處理食材與烹飪準備 須有相關經驗或相關科系畢業 依照勞基法排休輪休

1.處理房間安排事宜，如：訂房、排房、進房、退房等。 2.處理帳務，如：收款、核帳、查帳等。 3.負責轉接電話並且為客人留言。 4.提供當地旅遊諮詢，並協助安排旅行計畫、交通工具租用、接送等事宜。 需有相關經驗者，本飯店無提供宿舍 具備外語能力者另有獎金 供應員工餐

到職說明

上班時間為18:00-23:30(可彈性微調) 工作內容 1.湯屋清理。(整床、家具擦拭、浴室清洗、垃圾處理、備品補充等) 2.公共區域清潔。 3.客房定期保養工作。 4.協助客房服務:送備品.設備使用教學。

需配合輪班,無須輪大夜班 早班 7:00-15:30 中班 15:00-23:00

1. 管理客戶關係，定期拜訪現有客戶，開發潛在客戶並建立長期合作夥伴關係 2. 分析市場制定銷售計劃並提供決策建議 3. 負責銷售談判，包括價格協商與合約條款確定，達成銷售目標 4. 其他主管交代事項 歡迎您投遞履歷，加入我們的團隊，共同創造水產業的未來成就！

工作內容： 1.具備與ESL導師良好溝通能力以達成班級協同教學並創造良好的教學環境。 2.協助孩童完成當天作業內容，並注意字體工整及筆劃順序。 3.指導孩童國小課業內容，並針對個案給予加強。如：幫孩童複習國語、數學、自然等。 4.教導幼童良好的日常生活習慣及品德教育，培養幼童生活自理能力，並協助他人。 5.寒、暑假透過STEAM教學設計多元趣味課程，培養學生解決問題、展現自我能力。 5.完成其他主管交辦事項。 人才發展： 1.每學年協助老師針對工作上所需具備技能或者老師有興趣內容來開課。 2.學校資深老師陪伴教導，帶領新進同仁一起成長，達到教學相長的目標。 3.鼓勵老師在職進修領取相關證照，並配有完善學費補助制度。 4.完善的人才培訓制度及透明的升遷管道，提供有企圖心的老師一個發揮舞台。 職場福利： 1.配有電子app，協助老師快速完成親師溝通、點名、教學計劃等行政溝通事項。 2.完善軟硬體教學資源，提供SMART TV給老師更多元有趣的教學方式吸引孩童。 3.除員工聚餐，並配合各大節慶活動舉辦體系聯誼活動，EX:體系家庭日、中秋烤肉、聖誕交換禮物...等。 4.月薪外加6％勞退，並配有完善績效考核制度，逐年調整薪資。

工作地點：內湖麗山學區，單一學區（單純版本） ⏰工作時間： 週一～五12:00-8:00 週二2:00-7:30 ✅工作內容： 1.獨立帶班，熟悉國小一、二年級課程內容檢查作業、學科輔導、課室管理及家長溝通 2.寒暑假需配合帶營隊，可輪值 ☀️條件：大學畢，需至少3年以上獨立帶班經驗， 愛小孩、有耐性，做事細心，熟悉國小課綱及文書作業為佳 可以混齡獨立帶班薪資另議

職掌: 1.掌握產品市場新趨勢，掌握並提升產品的競爭力，提供內部人員專業諮詢與建議。 2.規劃產品策略、藍圖以及管理產品生命週期。 3.管理產品開發與量產之相關協調工作或技術移轉專案(包括專案規劃、專案組織成立以及開發時程、成本、品質等之控管等)。 4.採購核價、議價、下單、成本掌控及交期控制、進行驗收作業。 5.建立、更新供應商資料（如：貨品價格、規格和到貨時間），以選擇最佳供應商。 6.供應商維護及管理，與良好供應商維持良好關係。 7.開發新產品，新供應商蒐集，找尋品質好、成本低、配合度高的優良供應商。 8.提供緊急措施，使需求業務可做緊急採購。 9. 解決商品瑕疵退貨等問題。 10. 具備國貿、熟悉進口/三角貿易實務流程及採購流程。 11.語文能力(JLPT N1或N2檢定程度) 12.電腦能力(包含邏輯、組織、文書及簡報)、Vlookup&函數試算能力。 13.表達溝通能力(包含說服力) 14.普世價值:配合度、團隊合作特質 加分條件: 具品牌概念與代理品牌經驗。 公司官方網站 https://www.wonson.com.tw/zh-TW

***Please apply for this position on NXP official website: https://pse.is/8ms2kr Role Purpose Lead the development and optimization of high-voltage (HV) and BCD device architectures. This role requires a deep understanding of device physics and a data-driven approach to ensure industry-leading performance and reliability for power management solutions. Key Responsibilities － Device Development: Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes. － Physics Analysis: Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI). － Simulation & Modeling: Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles. － Device Verification: Define verification plans and execute statistical analysis using JMP for DOE and WAT data. － Design Integration: Work within Cadence environments for layout review and test structure design. － Cross-functional Collaboration: Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks. Required Qualifications － Experience: Master‘s or Ph.D. in EE, Physics, or related field with 10+ years of semiconductor industry experience. － Technical Expertise: 1. Profound knowledge of Device Architecture and Device Physics. 2. Hands-on experience in 180nm to 55nm BCD process nodes. － Tools: 1. Expertise in TCAD (Sentaurus / Silvaco). 2. Expertise in JMP for statistical data analysis. 3. Proficiency in Cadence (Layout/Virtuoso). Preferred Qualifications (Plus) － Advanced Power Devices: Experience with GaN, SiC, or IGBT development. － Silicon Photonics: Knowledge of Photonics integration and device physics. － Domain Knowledge: 1. Process Integration (PI): Understanding of mask flow and doping profiles. 2. Product Engineering (PE): Experience in CP/FT data correlation and yield enhancement. Competencies － Accountability: Strong ownership of project milestones and outcomes. － Critical Thinking: Ability to identify root causes in complex device failures. － Interpersonal Skills: Effective communication across design and foundry teams. － Data-driven: Committed to objective decision-making through rigorous data analysis.

The key areas of responsibility of the jobholder are: - Collaborate closely with foundries, NXP technology teams, and business lines to qualify and release advanced FinFET processes. - Provide technical leadership in semiconductor device physics, especially in FinFET architecture and behavior. - Interface with internal and external stakeholders on critical development and transfer projects. - Lead and steer projects to meet timelines and business objectives. - Make key decisions on process integration, balancing technical, logistical, and strategic factors. - Support NTI process transfers within foundries and NXP joint ventures Requirements / preferences: - Bachelor‘s or Master‘s degree in Electrical Engineering, Physics, or related field. - Minimum 10 years of experience in semiconductor device engineering, with a strong focus on advanced logic/RF devices. - Proven hands-on experience with HKMG and FinFET technologies in production or development environments. - Deep understanding of semiconductor device physics, especially HKMG and FinFET. - Strong analytical skills in yield enhancement and electrical data analysis. - Fluent in English and Mandarin. - Demonstrated leadership in development, transfer, or ramp-up projects. - Excellent communication and influencing skills. - Proactive, pragmatic, and results-driven mindset. - Experience working with foundries and leveraging external manufacturing capabilities .

Please also apply through: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/Tape-Out-Engineer_R-10063230 Role Overview, Responsibilities, and Qualifications The Tape Out Engineer plays a crucial role in the semiconductor design process, serving as the final checkpoint before integrated circuit designs are sent for fabrication. This position is responsible for ensuring that all physical and logical design data meet manufacturing requirements and quality standards, working closely with design, program managers, technologists, and manufacturing teams to resolve issues and optimize outcomes. Key Responsibilities 1. Coordinate and execute the tape out process for semiconductor products, ensuring timely and accurate delivery of design data to manufacturing. 2. Verify design integrity by reviewing database and documentation, and addressing any discrepancies or errors. 3. Work collaboratively with cross-functional teams, including design, technologists, program managers, and process engineering, to resolve technical issues and optimize designs for manufacturability. 4. Ensure all deliverables conform to foundry requirements. 5. Maintain detailed records of tape out procedures, revisions, and outcomes for future reference and process improvement. Qualifications 1. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s preferred). 2. Experience with physical design tools (e.g., Cadence, Synopsys) and semiconductor manufacturing workflows. 3. Excellent attention to detail, problem-solving skills, and ability to work under tight deadlines. 4. Willingness to work with flexible working hours to support critical Tape-outs. Effective communication in English for collaborating across technical teams. This role is ideal for individuals with a passion for precision and innovation, seeking to contribute to the successful launch of leading-edge semiconductor products.

Please also apply on our platform: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/APAC-Foundry-Operations-Senior-Principal-Engineer_R-10062827 Job Description The APAC Foundry Operation team works with foundry partners on technologies which are evaluated and/or subjected to production. The key areas of responsibility of the jobholder are: - Lead the release and transfer of process options at foundries. - Close collaboration with foundries, NXP technology groups, the business lines and various other stakeholders to qualify and release process - Lead and steer the projects towards timely completion to support NXP business needs. - Main decision maker on subjects related to process integration, striking a good balance between the various dynamics in a project; not limiting to technical judgement, resource planning, project schedule, logistics, supplier relationships etc. The requirement fulfilling the job: - Bachelor or MSc in physics, material engineering or electrical engineering. In-depth knowledge of semiconductor physics, process development and manufacturing. - ＞10 years of experience with semiconductor process integration, working in foundries’ production or development teams. - Hands on experience in being a lead; leading teams with responsibilities in development, transfer or production projects. - All rounded knowledge on process integration, product testing, reliability testing, tapeouts, device physics will be needed in the discharge of duties as a project/ integration lead. - Good communication skills. - Pro-active working attitude, creative, pragmatic, enterprising and result driven. - Having the ability to influence and steer a discussion. - Familiar in managing/working with foundries, maximizing leverage from foundries.

- Data analysis to ensure handler work on baseline. Ex. MCBA, index time, temperature control and HW interface maintenance 資料分析確保機台運作在基準條件, 包含作動不順, 作動時間, 溫度控制, 及機台介面維護 - SOP, OCAP, PM document creation. 建立標準化流程,異常處理文件,及保養維護文件 - Responsible for the performance of handler. 負責機台性能及相關報告 - Handle the improvement project on handler. 持續進行機台的改善計畫 - Management recipes of handler and spare parts 機台參數管理及備品管理 - Provide technology and operation training to shift assistant engineer and operators in manufacture lines to support production smoothly. 訓練助理工程師與作業員以利生產線順利運作 - Co-work with worldwide handler team for evaluation/improvement 與其他機台團隊跨國合作, 導入評估, 問題改善