交大專區

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification.

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification. * (If manager) Manage the design architecture team, focusing on both technological advancement and talent development.

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications • Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements • Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement • Location: Hsinchu, Taipei, Singapore, USA

0. 基本英文文書能力 1. Responsible for establishing and improving software engineering relevant systems and automation mechanism 2. Responsible for improving software configuration management systems 3. Responsible for improving release automation systems 4. Responsible for improving Linux build environment

1. 負責多媒體與周邊裝置的軟體及韌體開發（包含框架、驅動程式及功能開發）。 2. 執行客製化晶片功能驗證。 3. 進行系統效能優化及問題分析。

1) 負責設計與定義先進4G、5G及6G通訊系統內數據擷取控制系統架構，以作到系統行為分析、系統效能優化，以及問題解決。 2) 開發、優化並維護數據擷取控制系統的底層驅動程式與軟體控制流程。 3) 研究並導入以AI為基礎的自動化工具，以強化問題診斷、異常偵測與數據分析能力。

1. 參加 IEEE 802.11 會議, 協助發展新的 wi-fi 規格並與將需求設計架構實現在聯發科 wi-fi chip 內 2. 設計 Wi-Fi Platform 與 STA 系統架構, 協助開發改善 performance, QoS 需求

1. Bus and Architecture design and RTL implementation of Smartphone chipset 2. ASIC and Smartphone SoC and mobile computing platform design. 3. System bus and mobile peripheral designs 4. SoC system performance analysis

負責MCU/MPU(Microprocessor Unit)平台之嵌入式軟韌體開發、驗證與維護 1.設計、開發和優化 MCU/MPU 的軟體，包括初始化/啟動程式碼、驅動程式和外設庫 2.與硬體工程師、系統工程師協作，完成軟硬體整合與驗證 3.分析並解決MCU/MPU應用開發過程中的技術問題

1. High Speed digital design implementation 2. Integration from RTL to gate level, including flow QC, timing closure and issue analysis & solving 3. Signoff on design with mixed-signal interface 4. Design methodology and integration flow improvement

Co-work with algorithm, digital/analog design, firmware, AI tool teams. 0+ ~ 10+ Years Experience in: Agentic AI Workflow/Tool Evaluation/Deployment Data Center & High-Speed SerDes Design Verification Plan & Project Execution Automotive Design Verification Plan & Project Execution 5G/6G Wireless Communication Design Verification Plan & Project Execution Satellite/NTN Communication Design Verification Plan & Project Execution Processor Platform/Peripherals Design Verification Plan & Project Execution Subsystem / System Level Design Verification Plan & Project Execution

1. 2.5D/3.5D package technology development​ 2. SoC/Memory heterogeneous integration package development​ 3. Package technology integration, NPI and MP​ 4. Project management​

根據不同專案使用的各種CPU架構: * Function validation * Margin characterization & validation * System stability validation * Power/VF/Benchmark characterization * Customer issue resolve

* 根據積體電路設計流程、半導體器件、良率提升等相關知識進行數據分析 * 建立人工智慧框架與工作流程，以提升數據運營與分析的生產力 * 與不同的內部及外部團隊溝通協作，提出策略建議

IC設計: 晶片整合 IP開發

1. 規劃NPU量產測試程式 2. 測試及驗證IC功能、性能以及功耗的分析改進 3. 分析測試資料及測試相關問題，並分析良率問題並改善 4. AVS low power 的設計

SOC Pre-Silicon 平台技術, 流程方法, 參考設計開發

1. 參與CPU IP電路設計弱點之檢視與審查。 2. 開發 CPU IP 電路穩定度之測試項目，以排查/篩選出電路弱點。 3. 制定 CPU 電源完整性與電源量產品質方法

負責設計並優化數位相機及影像信號處理領域之IC，與演算法團隊協作，共同開發領先業界的影像處理解決方案，應用於智慧型手機、平板、車用及家庭娛樂等高成長市場。 工作職責 : - 與演算法工程師協作，設計高效能影像信號處理（ISP）/電腦視覺（CV）電路 - 提供優化硬體方案，達成IC設計「黃金三角」：最小矽面積、極低功耗、最佳影像品質 - 負責RTL設計、模擬、驗證、邏輯合成與整合流程 - 參與專案系統架構與技術研討，提出創新設計方案 - 支援產品跨部門整合及技術溝通

需求分析、架構設計 - 分析來自客戶的需求 - 了解客戶的期待 - 同意或拒絕客戶需求 - 依據需求提出架構設計