清大專區

分析及優化手機 5G TestBed 平台的效能，包括以下項目 1. 整合與移植不同 Linux 平台 (Ex. Ubuntu, Cent, RedHat, ...) 2. 整合與應用 Intel/AMD CPU Accelerator API (Ex. Intel Core i9 9/10/12th AVX/TBB/MKL; AMD...) 3. 分析與調校系統整體效能 (Ex. Linux Kernel, Process, Thread, Peripheral(Ethernet/PCIe/...) Driver, ...)

- Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power. - Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. - Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. - DFT insertion, ATPG and gate-level simulation - Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). - Interact with Physical Design Engineers and provide them with timing/congestion feedback.

- RTL/Logic Integration and Verification - Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top level including SOC. - Use cdc tool to check RTL/SDC quality - Develop Power Intent Specification in UPF for the multi-vdd designs.

1. Define GPU compiler software architecture and interfaces. 2. Development/implement GPU compiler pipeline, linking and various optimizations/transformations. 3. Collaborate with Driver team, HW team to implement new API & HW features. 4. Collaborate with Driver team, HW team to improve/tune performance & power consumption. 5. Execute & deliver to meet milestones/schedules. 6. Analyze and debug code generation issues. 7. Analyze and influence future GPU architectures. 8. Construct reliable & trustable relationships across teams internally & externally. 9. The position can be located at Hsinchu or Taipei

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 3.執行或協助功秏量測, 與power model預估的功秏做校正 4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗

1. 先進製程(＜N5)的可測試電路實作流程開發 2. 先進製程(N4/N3)可測試錯誤模型的研究與實作 3. 針對超高速與超低壓電路錯誤模型的研究與實作 4. 量產測試dppm分析與除錯, 測試效率的改善 5. 系統軟硬體測試的分析與除錯

人工智慧處理器系統架構及RTL設計。 系統架構設計包含效能、功耗、頻寬、以及面積分析。並須負擔RTL開發與部分整合工作。

1. (內轉佳, 提供發揮舞台, 跨產品線工作流程最佳化) 2. 人格特質: 領導力, 積極正面帶領團隊完成任務 3. 工作範圍:數位SOC設計整合, 包含 - Package, Floorplan, IOMUX, Test-mode design - Clock/CTS/reset/mixed-mode/DFT architecture, design and verification - RTL design and deliver SDC according to IP spec and requirement - SOC/IP DCT/DCG/Fusion synthesis - STA/CDC/CCD/TV/LEC/nLint/CLP tool and task handling

開發手機/平板SoC模擬及分析平台， 從系統效能，功率消耗，溫度控制...等多重面向分析產品競爭力， 進而從系統角度優化硬體架構及軟體控制策略。

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

弱電工程丶電話總機丶 安裝丶維護工程師 用戶端電腦維護與及故障排除 伺服器硬體維護與設定安裝 網路設備維護丶問題故障排除 設備庫存管理

1.協助業務販售日本村田(muRata)被動元件與及日本廣瀨(HIROSE)連接器 2.解決RMA不良品issue 3.至客戶端Promotion產品資訊,提供客戶對產品的認識及專業 4.負責正確對應產品規格符合客戶需求

1.施作內容網路配線、監控、通訊、等工程施工 2.電話及網路佈線 3.需具備: 機車或汽車駕照 ******有弱電工程經驗者依能力程度給薪 ***** 也歡迎無經驗~ 加入我們

可靠度測試實驗室測試執行/製作報告/參加職訓教育

1. PON ONT/RG之系統軟體開發、整合及維護。 2. Embedded Linux。 3. Protocol開發(GPON、EPON、L2/L3 Protocols)

1. Linux/C程式。 2. 系統韌體程式相關。 3. Android Framework and driver Programming。

1. GPON router相關產品測試及技術文件撰寫。 2. 至客戶端進行產品測試。 3. 各項錯誤回報與追蹤。 4. 客戶問題回覆。

1.5G CPE / 5G ODU 硬體電路設計(含射頻、基頻電路設計)。 2.Fine tune、Layout、Test plan、Debug。

1. Software team management. 2. Familiar with Linux, Router, VOIP, TCP/IP & Wifi software developing. 3. Issue analysis. 4. Work with team to validate and resolve the issues.

1.負責銷售日本村田(murata)被動元件及HRS廣瀨電機連接器 2.負責新舊客戶ODM的設計開發及OEM案子的詢價索樣服務與維繫