清大專區

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

開發模擬以及PoC測試平台, 工作包括 - 實作分散式運算架構 - 利用Kubernetes container 管理架構 - 實作概念性驗證

Do you want to be part of a smart and passionate team of researchers, advancing artificial intelligence to the next level of end-user experience in their daily lives? MediaTek is seeking driven and brilliant young students to join our efforts by providing Internship placements. We are currently working to expand the frontiers of Deep Learning frameworks for Computer Vision and Natural Language Processing and we hope you can join us! The ideal candidate is open-minded, passionate about learning theory, and looks forward to both practical and challenging problems. • You will be working towards or recently have completed a PhD in a quantitative field such as Computer Science, Mathematics, Physics or Engineering. • You have a good knowledge of the foundations of Deep Learning and Neural Networks, including some experience with Machine Learning frameworks (Tensorflow, PyTorch, JAX) • You are a proficient scientific communicator. You are committed to your goals and working in a team. • You are eager to tackle the state of the art problems in the field. We want your ideas to shine! As a Deep Learning Researcher in our team, you will collaborate with our Researchers and with worldwide colleagues, stay up and above the state of the art, initiate with novel ideas, and develop them into algorithms and applications that make the real difference in everyday devices. You will also push your contribution by publishing at top-tier conferences, such as NeurIPS, ICML, ICLR, CVPR, ACL, ICRA, ACM.

1. WiFi/BT/GPS/FM connectivity IC驗證及系統應用 2. PMIC or PCIe 系統設計及驗證 3. Connectivity 系統性能優化及驗證 4. Connectivity參考電路設計及驗證 5. 協助客戶量產過程時提供技術支援

1. Develop systematic algorithms to alleviate design challenges, including implementation, process what-if assessment, system performance evaluation, in advanced nodes or package 2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies 3. Explore new EDA features and define improvement direction from MTK product requirements

1.Smartphone SLT軟體整合(C/Android) 2.Smartphone SLT量產測試自動化流程改善

1. 數位晶片設計流程與整合 2. 熟悉低功耗的設計流程(和架構)

1. 測試機台操作與管理. 2. 產品品質問題電性分析 3. 跨部門溝通以分析產品故障真因

1. FR-1 平台天線解決方案開發與驗證 2. 使用EM模擬軟體進行天線解決方案性能評估 3. 與跨部門團隊合作開發新MTK平台天線解決方案

1. 規劃量產測試以及量產functin pattern porting 2. 測試以及驗證IC功能，性能，以及功耗等等相關測試 3. 分析測試資料以及釐清相關測試的問題，並分析良率問題以及良率改善建議 4. AVS low power的設計

先進封裝技術開發 1. 先進新產品導入技術開發 (新產片試產規劃, DRC/DRM檢驗, DOE及良率改善規劃, 量產區間及良率分析) 2. 熟悉先進chiplet及3DIC封裝技術開發 3. 晶圓級與面板級先進封裝結構設計

1. 開發emulation/prototyping 相關的技術及使用流程 2. 建立CPU/GPU emulation/prototyping 驗證平台 3. 協助project team導入emulation/prototyping 技術 4. emulation/prototyping 使用及工具問題的支持 5. 管理 emulator 及prototyping 硬體與使用分配

1.CP/FT testing flow development & verification 2.Product manufacturing yield analysis & improvement

熟悉高速類比serdes 電路設計 例如 CTLE, CDR, DFE, PLL以及TX driver等

5G modem系統驗證規劃, 資源安排與專案管理

1. Perform pre-silicon and post-silicon correlation and modeling related to adaptive voltage scaling and on-die sensor 2. Develop and improve post-silicon testing methodologies related to adaptive voltage scaling and on-die sensor

1.設計測試硬體配件 2.IC驗證 3.CP/FT 測試程式開發 4.量產維護

1. 高速信號介面及系統電源應用規劃整合、除錯等手機系統應用. 2. Baseband系統驗證方法開發、電源規格訂定及驗證規劃 3. 客戶參考設計文件訂定及量產相關技術支援.

SoC測試助理: 負責MediaTek手機平板車用在系統上的測試與測試工具開發

28nm及以下先進製程(含FinFET) IO電路和ESD防護設計, 工作內容包含 (1) GPIO電路設計(包含ESD/LU防護) (2) 特殊應用IO (SD3.0/SIM card/eMMC等)電路設計(包含ESD/L防護) (3) 高速IO和特殊應用IO在事業部專案上展開和執行 - Advance node (28nm and beyond, including FetFET) IO circuitry and ESD protection design covering fields for (a) General purpose IO circuit design (with ESD/LU protection) (b) Specialty IO (SD3.0/SIM card/eMMC etc.) circuit design (with ESD/LU protection) (c) Project related implementation for high speed/specialty IO Interface - High speed IO, specialty IO circuit design, ESD protection circuit design and simulation. Work with project leader, layout, packaging and system engineers to meet design and system specifications. Work with IO library modeling, characterization teams closely for IP release.