清大專區

1. Interpret customers’ functional safety requirements 2. Derive functional and technical safety concepts from functional safety requirements 3. Develop and review the safety IP design 4. Communicate and coordinate safety designs with IP teams 5. Perform system safety analysis (ex: FMEDA)

解讀客戶的網絡安全需求 從網絡安全需求中推導出功能和安全概念 制定和審查安全系統架構 與 IP 團隊和客戶溝通和協調安全設計 執行系統安全分析（例如：TARA）

1. 開發設計 Security HW IP 2. 協助 HW IP 驗證 3. 執行 IC 設計整合流程

解讀客戶的網絡安全需求 從網絡安全需求中推導出功能和安全概念 制定和審查安全系統架構 與 IP 團隊和客戶溝通和協調安全設計 執行系統安全分析（例如：TARA）

1. Define power states and management hardware architecture for optimal power performance. 2. Design microprocessor-based power management controller and HW assistance designs. 3. Define power architecture by performing power rail tradeoff analysis with adaptive voltage scaling consideration

1. Develop and implement tailored DRAM controller/PHY solutions for automotive applications. Validate functionality, improve design revisions and meet performance targets as well as system requirements. 2. Perform rigorous design testing and debugging in automotive environments. Troubleshoot and propose solutions for any issues occurring in post-silicon validation. 3. System Level Cache Design & Implementation: Design and implement system level cache strategies to optimize performance and efficiency across our product range. 4. System-Level Understanding: Exhibit a system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.). 5 . Ensure that all designs comply with automotive industry standards and regulations, such as ISO 26262 and Automotive SPICE.

We are seeking skilled engineers for designing high-performance Virtualization and Interconnect Architecture and developing RTL for both Automotive and High-Performance Computing. Roles: 1. Develop, assess, and refine RTL to achieve performance, power, area, and timing goals. 2. Develop micro-architecture by exploring early high-level macro architectures, researching micro-architecture, and defining detailed specifications. 3. Coordinate co-design efforts between architecture, software, and hardware teams to achieve functional realization. 4. Develop and implement interconnect methodologies, such as simulation, emulation, implementation, and efficiency improvement.

1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit.

1. Implement and maintain device drivers, or firmware for high-speed interfaces, such as PCI Express, MIPI CSI-2, USB or UFS. 2. Develop FuSa and security software framework for high-speed interfaces to fulfill automotive requirements.

1. Develop scalable platform clocking architecture for automotive SoC 2. Enhance SoC clock architecture and technology development to address the automotive SoC requirements 3. Drive clock architecture and designs to optimize power, performance, and implementation, including physical design and timing closure

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

1. Responsible for the development of soft firmware of ASIC product system, high-speed data transmission Software/PHY development and optimization of hardware performance 2. Lead related IP development, familiar with software/firmware/SDK, issue debugging, optimization and testing in ASIC projects 3. Collaborate with the team for functional/system bring-up, validation, performance optimization and adjustment 4. Achieve product design-in import and support product mass production 5. It would be better if being capable in Signal Processing/Algorithm implementation and SI/PI simulation interpretation.

1.Digital design (RTL design, Synthesis, integration, verification) 2.SoC Chip design, integration 3.Familiar with VLSI design flow is a plus

1.Collect the safety design spec for the camera/display/audio subsystem and build the execution plan for safety design verification 2.Co-work with IP design verification teams to achieve pre-silicon verification of hardware safety requirements 3.Deploy fault simulation for safety IPs

1.Develop fault simulation flow for function safety. 2.Deploy fault simulation for safety IPs 3.Co-work with IP design verification teams to achieve pre-silicon verification of hardware safety requirements

We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

• 此職位屬於聯發科技modem客戶工程團隊，該團隊任務為與內部研發團隊合作，支援全球一流智能手機客戶的無線通訊技術(包括LTE、5G Sub-6GHz和5G mmWave技術)。 • 此職位主要職責在與客戶合作過程中帶領技術討論，並與內外部不同團隊合作，共同討論並解決客戶問題、滿足需求。 • 此職位需具備深入研究技術問題、了解客戶需求分析與功能開發的能力及良好應變能力。 • This is an exciting role in the MediaTek wireless technology group within the modem customer engineering team working with internal R&D team and support tier-1 global smartphone customers in wireless technologies (LTE, 5G Sub-6GHz, and 5G mmWave technologies) • You will play a key technical role in working with internal and external stakeholders to lead technical discussion and drive customer issues to resolution. • This is a dynamic position that will interact and collaborate with different teams and site location. • Ability to deep dive technical issues, understand customer requirement analysis and feature development. Looking for 4G/5G Modem Protocol / System Engineer with technical breadth in the protocol stack.

由於先進製程與高整合度晶片需要較長的研發時間及高製造成本，DV (Design Verification) 已成為聯發科技晶片開發流程中不可或缺的一環。 CDG DV部門負責開發與執行最高整合度 Smartphone，TV與ASIC驗證工程。 內容包含:整合型驗證環境開發，大數據分析與效能改善，BUS Fabric / EMI (External memory interface ) / Low power functions 驗證規劃及執行。 工作中需要設計及精進Verification plan/methodology/bench，對SOC系統有整體而深入的了解。 利用最新EDA tool and concept來完成你的驗證計畫。 工作地點:新竹/台北

1. Work with design teams to do performance sign off in pre-silicon stage 2. ESL platform and simulation/emulation technology development. 3. Model development (includes behavior modeling/ cycle approximate modeling)

1.PCB 電路及layout 的設計及驗證 2. 客戶端平台之開發驗證