清大專區

We are heavily recruiting talents and professionals in DV, EDA, and AI/ML fields to join our force to conquer new heights in chip complexity! As one of the world’s top IC design companies, MediaTek is constantly pushing the capabilities of chips to the limits. Our newest SoCs and ASICs are wildly sophisticated, packed with industry-leading technologies built by thousands of chip designers. With great design power comes great verification responsibilities. Our team, as a part of the verification force, has put major efforts into creating innovative and robust strategies to fulfill these responsibilities. To ensure high design quality for first silicon success, we have implemented a complete suite of functional and low-power test plans and benches across all design scopes, from IPs to SoC integrations. Furthermore, we have been collaborating with EDA tool providers and academic institutions on leveraging new verification technologies, including emulation, AI tuning, and formal methods, many of which have improved the traditional workflows by orders of magnitude. We also keep challenging ourselves to develop in-house verification tools and platforms to accelerate test regressions and track verification progress more efficiently. All these efforts ultimately lead to our success in delivering high-quality chips over the years.

1. 高速SerDes IP開發 2. 數位電路設計與晶片整合 3. 訊號處理與通訊演算法實現

1. 記憶體電路設計與驗證 2. 記憶體編譯器平台開發

電磁干擾設計工程師主要負責射頻與類比電路信號完整性 (RF/Analog signal integrity) 、電磁干擾 (EMI/EMC) 分析與及封裝天線 (Antenna-in-Package) 設計。藉由開發”晶片+封裝+印刷電路板”共設計流程來解決高整合數位/類比電路的干擾問題，以提供客戶高性價比的 RFSOC/RFSIP 無線通訊 (cellular 4G/5G) 及無線連結 (WiFi, BT, GPS, FM radios) 產品。 1. 射頻與類比電路信號完整性分析與設計 2. 射頻系統單晶片 (RFSOC/RFSIP) 電磁干擾分析與設計 3. 封裝天線設計與驗證 4. “電路+封裝+印刷板” 共模擬平台開發與驗證 5. Design Guide 的撰寫與推廣

高效能/低成本/低功耗/高效率，具延展性的階層式Smartphone SOC on chip bus 構架設計

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis and post silicon debugging 2. Low power analysis, including pre-silicon power model creation and big data analysis 3. SoC architecture exploration and performance analysis experience is plus

高速與低功耗GPU實作(P&R), Power/Performance/Area/Schedule改善及FLOW開發 The candidate who fills this position will work closely with GPU hardware designer, IP and flow teams to improve GPU power/performance/area/schedule/yield. Candidate is responsible for all aspects of physical design and implementation of large GPUs which are targeted at the DTV, smart phone markets. Responsibilities include GPU hierarchical physical implementation/coordination (floor plan, block assembly, power/clock distribution, timing closure, power, IR, noise analysis and back-end verification). Also responsible for flow development with focus on improving GPU development schedule, chip cost, chip power, chip performance, yield, and development resources.

【職缺一】APR實體設計工程師 1. Working on advanced node design methodology, PD execution and sign-off 2. Develop advance clock tree structure 3. Able to handle complex APR with 500+ hardmacros 4. Project analysis in early stage 【職缺二】超大型SoC實體設計工程師 1. executing ultra-large scale SoC hierarchical physical design, in TOP level or GHz complex block level 2. Full experienced PD who can manage/coordinate other PDs‘ various number of hierarchical blocks 3. Flow development experience is a plus, to consolidate ultra-large scale SoC methodologies

對數位電路設計有熱忱者，負責 IP 開發, 整合與偵錯

• 參與3GPP RAN4會議，包括可能的線上或線下討論，以及協助撰寫會議技術文稿 • 檢驗內部及外部標準提案的有效性，透過鏈路級模擬或系統級模擬來撰寫技術文稿 • 於鏈路級模擬或系統級模擬程試中開發新的模組來支援最新3GPP標準的功能 • 參與內部或外部會議，提供想法創意，以及所需之效能評估

- Explore timing degrade considering power integrity for proper signoff criterion - Explore EDA tool new features and introduce to project team - Define area-efficient stacking possibilities, robust PG structure for different IP styles - Provide quick assessment to IR severity and improved approaches

1. WiFi 無線通訊系統架構 2. WiFi IP數位設計 3. 計算機系統與周邊架構與數位設計 4. 系統晶片整合

1. Work on 28nm~7nm design implementation, methodology, and sign-off 2. Perform floorplan, clock planning, place and route, timing closure, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution 1. Work on 28nm~7nm design implementation, methodology, and sign-off 2. Perform floorplan, clock planning, place and route, timing closure, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. Architecture design and RTL implementation of Camera system 2. Verification of Camera system

1. 影像編碼器硬體架構研究與電路設計實現 2. 影像編碼演算法研究與硬體複雜度分析

1. ARM CPU subsystem platform design & integration 2. CPU post-silicon issue resolving

1. 執行功能與性能測試工作,並操作對應的測試儀表. 2. 與同事合作共同定位, 分析與解決測試過程中發現的問題.

1. Smartphone功能開發流程設計及管理 2. 需求管理流程設計及管理 3. 內部project feature管控 1. Smartphone feature development process design & management 2. Requirement management process 3. Internal project feature management and control

1. WiFi 無線通訊系統架構 2. WiFi IP數位設計 3. 計算機系統與周邊架構與數位設計 4. 系統晶片整合

1. Processor ISA design 2. Cache and bus interface 3. DSP and machine learning library design 4. Simulator/modeling and architecture