研發替代役專區

1. 負責相關物料及成品倉庫的進出管理。 2. 物料請購(需會基本的EXCEL)。 3. 維持倉庫的整潔與組織性。 4. 定期進行物料庫存盤點，更新系統記錄，並確保盤點數據的準確性。 5. 協助出貨系統（新竹貨運系統）出貨單建立，並完成出貨產品的安全包裝及裝箱程序。 6. 熟練操作手排貨車(需協助物料運輸至倉庫)。 7. 公司有2位倉管可相互配合，上述工作皆與部門同事調整分配。 8.執行主管分配的其他相關任務。

1.客房清潔以及備品作業。 2.樓層保養作業及備品倉儲作業。 3.負責工作區域清潔工作。 4.負責日常清潔保養工作。 5.執行其它清潔相關交辦事項。

工作內容: 與工廠確認打樣及修版工作進度。 樣衣細節確認及商品品質流程追蹤。 會議記錄／版型確認／檔期安排 進度追蹤／出貨調度／訂單溝通 工作需具備: 需有基礎服裝打版基本知識與熟悉成衣生產製造流程。 耐心與責任心更是不可缺，且能保持創新的動力。

1.機械設備保養維修。 2.現場生產設備異常排除。 3.現場工具列管。 4.具水電、機電控制基礎知識者佳。 5.完成主管交辦事項及報告製作

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

* Define and optimize SOC hardware architecture and associated software flows in aspects of system performance/power/area to improve MediaTek‘s product competitiveness. * Develop simulation and analysis platforms for performance/power/area analysis. * Work Loction : HsinChu, Taipei

1. (內轉佳, 提供發揮舞台, 跨產品線工作流程最佳化) 2. 人格特質: 領導力, 積極正面帶領團隊完成任務 3. 工作範圍:數位SOC設計整合, 包含 - Package, Floorplan, IOMUX, Test-mode design - Clock/CTS/reset/mixed-mode/DFT architecture, design and verification - RTL design and deliver SDC according to IP spec and requirement - SOC/IP DCT/DCG/Fusion synthesis - STA/CDC/CCD/TV/LEC/nLint/CLP tool and task handling

開發手機/平板SoC模擬及分析平台， 從系統效能，功率消耗，溫度控制...等多重面向分析產品競爭力， 進而從系統角度優化硬體架構及軟體控制策略。

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. Leading and integrate team members and technology of analog IP to engage new SOC products including multi-vertical product lines. 2. Work as analog project management team and work closely with SoC Integration teams responsible for enabling on-time silicon to meet product schedules. 3. Multi-task skills will be key to lead several tasks of project at a time. 4. Track and drive resolution of technical issues between multi-functional teams including Design, Verification, Validation, Process Technology, Packaging, Quality and Reliability, System Hardware and Application Convert data into a clear story to communicate to partners and organizations at all levels. 5. Also, as good communication bridge between Analog and SOC Regular project status presentations for executive leadership review including issue report, bug tracking, risk assessment and mitigation plan.

1. Product planning, marketing, promotion and project design-in 2. Market analysis and Business Strategy 3. Customer relationship management

MTK電源管理部門設計設計電源管理IC及電源管理單元以滿足各式各樣智慧手機, IOT, 車用, 以及ASIC的需求. 職缺包含: 1. DC-DC 轉換器 2. 線性電壓調節器 3. 切換電壓調節器

協助電源管理晶片規格製定, 新 IP 開發規劃及產品驗證協助類比晶片IP開發, 驗證.

高速類比 SerDes 電路設計 Work Location : 新竹/竹北/台北/台南

This position involves developing memory architectures, creating circuit implementation techniques and be an interface with CAD team for full verification and model generation. You have opportunity to know how memory design can be implemented into all Mediatek products.

1. 開發, 優化與維護 4G/5G Modem 自動化整合測試平台, CI Flow 等. 2. 開發, 優化與維護 4G/5G Modem Simulator 3. 開發, 優化與維護 4G/5G Modem 研發流程與驗證平台的 Tool Chain

分析及優化手機 5G TestBed 平台的效能，包括以下項目 1. 整合與移植不同 Linux 平台 (Ex. Ubuntu, Cent, RedHat, ...) 2. 整合與應用 Intel/AMD CPU Accelerator API (Ex. Intel Core i9 9/10/12th AVX/TBB/MKL; AMD...) 3. 分析與調校系統整體效能 (Ex. Linux Kernel, Process, Thread, Peripheral(Ethernet/PCIe/...) Driver, ...)

- Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power. - Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. - Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. - DFT insertion, ATPG and gate-level simulation - Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). - Interact with Physical Design Engineers and provide them with timing/congestion feedback.

1. Define GPU compiler software architecture and interfaces. 2. Development/implement GPU compiler pipeline, linking and various optimizations/transformations. 3. Collaborate with Driver team, HW team to implement new API & HW features. 4. Collaborate with Driver team, HW team to improve/tune performance & power consumption. 5. Execute & deliver to meet milestones/schedules. 6. Analyze and debug code generation issues. 7. Analyze and influence future GPU architectures. 8. Construct reliable & trustable relationships across teams internally & externally. 9. The position can be located at Hsinchu or Taipei

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 3.執行或協助功秏量測, 與power model預估的功秏做校正 4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗