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Sr Analog Circuit Design Engineer-pure analog_IC設計公司 (3010251)

Accurate愛客獵股份有限公司(1111 高階獵才)

新竹市東區

職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

Accurate愛客獵股份有限公司(1111 高階獵才) 位於台北市松山區南京東路五段89號14樓

新竹市東區

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