交大專區

1.Lead the development and enhancement of RC extraction flow for advanced physical designs 2.Drive RC extraction flow development for heterogeneous integration technologies, including CPO and 3DIC 3.Collaborate with EDA vendors to advance RC extraction methodologies 4.Perform FOM RC analysis to identify and propose DTCO opportunities

1. WiFi/BT/UWB 公板設計及驗證 2. PCB 公版設計, 除錯, 驗證 3. FCC/CE/TELEC EMI 防治對策 4. 支持客戶應用及量產導入

1. 4/5/6G modem hardware architecture and digital circuit design task 2. Define hardware architecture of a digital IP/system 3. Include Clock, Bus (AXI/APB/NOC/…), Async design, high speed IF, new IP for sub-sys design topic 4. IP and Subsys digital design and PPA optimization 5. Subsys integration from RTL to gate level including timing closure and testability 6. Design methodology and integration flow improvement

職責要求 1.新產品開發(NPD)：主導高速網路線、網路跳線（Patch Cord）及箱線（Bulk Cable）之結構設計、規格制定與打樣開發。 2.製程與技術優化 3.高頻訊號分析 4.跨部門與工廠對接推行並落實QA管理制度 任職資格 1.具備5年以上線纜（Cable）或連接器（Connector）產業研發經驗，其中須包含至少 3 年以上的研發團隊管理經驗。 2.英文能力 TOEIC600 以上

1. 軟硬體協同設計：參與早期規格或硬體系統定義，從軟體觀點提供優化建議。 2. 關鍵技術解決：編寫核心原型代碼，解決效能瓶頸等複雜系統級別問題。 3. 技術指導：提升團隊架構思維與技術實力。

•重點開發技術: 系統開發、高速資料實體層(physical layer) 資料傳輸軟體開發、優化硬體效能及產品量產品質控管 •主要目標: 完成Enterprise/AI/xPU等相關產業客製化IC的軟韌體開發與系統整合，並協助客戶產品量產，有SLT的經驗 •負責新產品的系統設計與開發，確保符合公司及客戶的需求 •協助量產過程中的技術問題解決，並提供專業建議以提升生產效率與品質 •與跨部門團隊合作，確保產品從設計到量產的順利過渡 •分析並改善現有系統和流程，以提高產品質量和生產效率 •參與產品測試和驗證，確保產品符合相關標準和規範

• Lead GPU verification efforts across unit, subsystem, and full-chip levels, partnering closely with GPU architects, RTL design leads, performance engineers, modeling teams, and software/firmware teams. • Develop a deep understanding of GPU specifications and microarchitecture, including the 3D graphics pipeline, compute workloads, shader cores, memory hierarchy, cache/coherency, command processing, scheduling, and control subsystems. • Define the overall verification strategy, methodology, test architecture, milestones, and quality metrics for assigned GPU IPs and/or top-level GPU integration. • Drive creation and execution of comprehensive verification plans, ensuring traceability from architectural and RTL specifications through test implementation, functional coverage, assertions, and closure. • Lead development and maintenance of scalable SystemVerilog/UVM verification environments, including reusable agents, BFMs, scoreboards, reference models, checkers, and HW/SW co-simulation infrastructure. • Guide the team in developing directed, constrained-random, stress, error-injection, and scenario-based tests for graphics, compute, memory, and control features. • Drive functional and code coverage closure through rigorous coverage analysis, identification of verification gaps, and creation of targeted tests for corner cases and late-stage bug escapes. • Own regression health for the verification scope: establish regression strategy, monitor quality metrics, prioritize failures, coordinate triage, and drive root-cause resolution with design and architecture teams. • Review verification plans, testbench architecture, test code, coverage models, and debug approaches; provide technical mentorship and guidance to DV engineers. • Partner with performance, architecture, and design teams to develop performance-verification workloads, execute emulation/prototyping runs, analyze bottlenecks, and support performance, power, and area (PPA) optimization. • Drive efficient debug of complex RTL, testbench, firmware, and HW/SW co-simulation failures, clearly communicating root cause, impact, and resolution plans to cross-functional stakeholders. • Collaborate effectively across geographically distributed teams and communicate verification status, risks, and closure plans to project leadership.

參與 5G/6G New Radio 行動通訊數位基頻 IC 與 IP 開發. 包括multi-RATs (2/3/4/5/6G) modem的架構設計, RTL 設計, 整合和驗證.

1. Optimize 6G/5G modem architecture and associated hardware/software flows in aspects of system performance/power/area (PPA) to improve product competitiveness. 2. Develop architectural simulation, system-level modeling, and analysis platforms for modem baseband system performance, low-power optimization, and hard real-time (HRT) latency analysis. 3. Collaborate closely with domain architects to deliver quantitative reports based on simulation data, driving key architectural decisions. 1. 優化 6G/5G 解調架構及相關的硬體/軟體流程，提升系統效能／功耗／面積（PPA），增強產品競爭力。 2. 開發架構模擬、系統級建模與分析平台，用於評估基帶系統效能、低功耗優化與硬實時（HRT）延遲分析。 3. 與領域架構師緊密合作，根據模擬數據產出量化報告，推動關鍵架構決策。

我們的使命是協助公司將生成式 AI（Generative AI）有效導入日常工作流程，推動員工提升工作效率與創新能力。 此職位將擔任技術團隊與業務單位之間的橋樑，協助規劃 AI 導入策略、設計賦能活動、推廣最佳實務，並蒐集使用者需求與回饋，持續優化 AI 工具的應用成效。 我們期待對 AI 技術充滿熱情，具備優秀溝通能力與推動能力的人才，一同加速企業 AI 轉型。

• Lead FPGA development activities across functional prototyping, emulation, performance evaluation, and database generation flows. • Work closely with architecture, design, verification, software, firmware, and performance teams to understand system requirements and define FPGA implementation strategy. • Drive FPGA functional flow, including RTL integration, FPGA partitioning, synthesis, place-and-route, timing constraints, timing closure, bitstream generation, bring-up, and debug. • Drive FPGA performance flow to support in-house performance evaluation, workload execution, data collection, profiling, and performance database generation. • Design, implement, integrate, and optimize FPGA logic using Verilog/SystemVerilog/VHDL. • Develop and maintain FPGA prototypes and emulation platforms for system validation, software enablement, firmware development, and hardware/software debug. • Support performance analysis by enabling representative workloads, collecting runtime metrics, identifying bottlenecks, and collaborating with architecture/design teams on improvement opportunities. • Define and improve FPGA methodology, automation, build flows, regression infrastructure, and debug processes for both functional and performance use cases. • Support and integrate interfaces such as PCIe, DDR, AXI, Ethernet, SPI, I2C, UART, and other standard protocols. • Provide technical leadership, mentor engineers, coordinate cross-functional execution, and drive issue resolution across multi-site teams.

1.Propose design verification plan and do the execution based on IP and system HW architecture/application 2.Develop design verification environment 3.Develop required verification methodology and adopt into project 4.Develop HW emulator/FPGA platform to accelerate design verification task 5.Co-work with SW/HW engineering to valid function and shift-left SW develop 6.Debug and root cause failure with SW/HW engineering in both pre-silicon and post-silicon

1.RTL platform design integration (clock/reset/power/bus design and architecture, MBIST, etc.) - use for FPGA and Emulator should also be considered 2.Integration quality check (RTL/SDC/Power spec signoff check)

1. Processor micro-architecture design 2. Cache and bus interface 3. DSP and machine learning library design 4. Simulator/modeling and architecture

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow

1. Lead or support SoC architecture design, modeling, and technical feasibility studies across specific domains, including cellular modem, connectivity (Wi-Fi/Bluetooth/GNSS/UWB), performance, and power. 2. Lead or support SoC architecture development for smartphone, thin-modem, CPE/telematics, and gateway products, focusing on system performance and power considerations based on product requirements. 3. Lead or support technical feasibility studies of product requirements and collaborate with domain architects and product marketing teams to develop competitive product specifications.

1 Develop the Timing/EM signoff criterion for leading process node and 3DIC. 2 Maintain the Timing/EM Signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing/EM violation 3 Develop new Timing/EM signoff methodology to be applied during chip synthesis/APR/STA/EM . 4 SPICE correlation for new timing/EM signoff criterion 5 Regression test for every signoff methodology by STA violation/slack analysis, EM results 6 Post-silicon data analysis for silicon-proven timing/EM signoff criterion

Senior Technical Program Leader | USB3/USB4 Customer Issue Resolution

1.WiFi/BT Reference board design, system integration and verification. 2.Capability for PCB circuit layout/debug/develop. 3. Dealing with EMI issues 4. Dealing with high-speed digital interface issue

我們正在尋找一位具備先進製程元件特性量測與 SPICE 元件模型經驗豐富的工程師。 * 驗證 SPICE 模型並追蹤來自晶圓廠的模擬與實測 (S2S) 一致性 * 執行廣泛的元件特性量測與分析，以利製程與元件評估及基準比較 * 建立符合內部需求的客製化內部模型 * 為設計人員提供元件與 SPICE 模型相關的諮詢與指導方針