交大專區

1) 訂定通訊系統使用的CPU及系統架構 2) 開發RTOS、記憶體管理等系統相關服務 3) 開發CPU及平台模擬器 4) 分析軟體行為並增進系統效能 5) 開發CPU及系統相關的驅動及開機流程 6) 開發自動診斷系統問題的工具

We are looking for experienced ML/DL candidates to join our team of PhD-level researchers and interns. The ideal candidate is open-minded, passionate about pushing learning theory, and keen on the opportunity to challenging convention. In a flexible and supportive environment, one of your major responsibilities is to push the state of the art of learning theory, to obtain insights beyond mythical theories as well as to apply the right solution to novel application areas such as AI-designed IC and General Intelligence Conversation. Furthermore, you shall actively engage with worldwide colleagues and academics to nurture and build a collaborative and effective R&D environment. We welcome all ML/DL backgrounds, including computer vision, speech and NLP, and robotics.

1. CoWoS和2.5D封裝技術開發 2. 3D封裝技術開發 3. CPC/CPO封裝技術開發 4. 封裝技術整合和NTO管理

1. Package related structure stress analysis including warpage, material study. 2. Package and board level stress modeling for TCT, drop and vibration. 3. IC and package thermal analysis, modeling and characterization 4. Chip-Package-PCB thermal co-simulation and design. 5. System level thermal simulation 6. System level stress simulation

1. 先進製程技術製程開發 2. 先進封裝技術開發

職缺說明 我們是聯發科技IT MLOps平台團隊，致力於打造高效、可擴展的MLOps平台，提升企業AI模型開發、部署與運維自動化能力。團隊積極導入最新技術並持續學習成長，尋找具備MLOps平台架構設計與實踐經驗的菁英，一同推動公司AI數據驅動轉型。 歡迎對雲端/地端AI平台、機器學習自動化與大型系統架構有熱情的你加入我們！ 工作內容： 1 規劃並設計企業級MLOps平台架構，負責專案規劃、目標訂定、技術選型與落地執行。 2 與跨部門團隊AI合作，協助把商業問題拆解為可自動化實現的AI工作流，支撐AI模型端到端生命周期管理。 3 主導平台核心模塊建置：模型訓練/部署管線、CI/CD for ML、資料流通與版本控管、模型監控與資產管理等。 4 推動企業級MLOps標準化、流程自動化與最佳實踐，優化模型運營效能、穩定性及安全性。 5 參與平台持續優化與技術創新，導入新技術·新工具如Kubeflow、MLflow、Vertex AI等，提升平台功能。 6 協助建立團隊技術文化，分享MLOps相關知識、推動內部技術培訓與交流。

Product 2.5D/3D/3.5D heterogeneous package development, LPDDR/HBM/IPM development for advanced package, product memory roadmap, package memory architecture , customized HBM development

【職務概述】 我們正在尋找具前瞻視野與創新精神的工程領導者，加入生成式 AI 應用平台團隊，打造企業級 GenAI 平台，協助內部團隊快速開發 AI 應用與智能代理，推動數位轉型。您將領導團隊建構關鍵能力，包括 RAG 框架、多代理分析平台與 HyperAutomation 模組，並推進多代理協作、模型路由、LLMOps 標準化與負責任 AI 治理。 【主要職責】 策略與領導：帶領跨領域團隊，制定技術藍圖與 KPI，導入 RAG 2.0、知識圖譜、AI Agent 協作等技術。 平台研發：設計與維運 RAG 框架、多模態分析 Agent、AI 自動化模組，導入 MCP、LangGraph 等前沿技術，強化平台效能與治理。 利害關係人協作：作為技術策略夥伴，協助事業單位導入 GenAI，與資料、業務、安全團隊共創 AI 解決方案，推動開發者生態與負責任 AI 架構。

1. CPU/GPU STA, high-speed & low-voltage timing signoff/ timing closure 方法流程設計 2. STA 流程開發及應用 3. high-speed/low-voltage timing signoff criteria開發及應用 4. 針對project的STA/timing signoff問題進行分析及改善

負責 SoC／系統層級的效能與功耗分析、優化。 與硬體、韌體、軟體、架構等團隊合作，推動效能與功耗改善方案。 針對系統瓶頸進行深入分析，提出有效的優化解決方案。 參與 DVFS、低功耗設計、系統資源管理等技術的開發與調教。 針對 Windows 平台，優化 Windows PPM（Processor Power Management）設定，提升系統效能與功耗表現。 分析並調教 Windows Power Management 相關設定，確保系統在各種使用情境下達到最佳效能與最低功耗。 撰寫技術報告與文件，並提供內部團隊及客戶技術支援。

1.數位電路設計 2.多媒體架構與電路設計 3.多媒體系統整合 1.Digital IC Design 2.Multimedia Architecture and Design 3.Multimedia System Integration

1. Architecture design and RTL implementation for Smartphone and automotive chip 2. Smartphone SoC and mobile computing platform design. 3. System bus and high speed interface designs

解讀客戶的網絡安全需求 從網絡安全需求中推導出功能和安全概念 制定和審查安全系統架構 與 IP 團隊和客戶溝通和協調安全設計 執行系統安全分析（例如：TARA）

1. Responsible for the development of soft firmware of ASIC product system, high-speed data transmission Software/PHY development and optimization of hardware performance 2. Lead related IP development, familiar with software/firmware/SDK, issue debugging, optimization and testing in ASIC projects 3. Collaborate with the team for functional/system bring-up, validation, performance optimization and adjustment 4. Achieve product design-in import and support product mass production 5. It would be better if being capable in Signal Processing/Algorithm implementation and SI/PI simulation interpretation.

1.CPO SERDES 系統開發​ 2.CPO Optical系統開發

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

1. 負責高速 Serdes相關開發, 包含驗證, 客戶支援 (熟悉架構, 韌體、除錯、優化及測試等工作項目) 2. 開發測試自動化 3. 協同團隊共同完成系統雛型建立及性能優化與調適 4. 達成客戶端產品導入，並支援產品量產

1. Serdes PMA IP architecture planning 2. Serdes PMA IP RTL coding 3. Serdes PMA IP front-end and back-end integration 4. Co-work with PCS and MAC design team and DV team for IP verification 5. Co-work with Analog design team for PHY co-simulation 6. Co-work with Algorithm team for algorithm implementation and bit-true verification

1. IEEE 802.3 Ethernet PHY & transceiver architecture & algorithm design 2. Digital signal processing of mixed-signal design 3. System simulation/model design for pre-silicon verification 4. System & algorithm design/simulation of high-speed I/F SerDes 5. Make contribution in standard organizations

1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams