交大專區

1. 優化相機、影音播放與編輯等多媒體架構，最大化系統效能與使用者體驗。 2. 分析 SoC 效能瓶頸並執行系統調優，提出軟硬體架構優化策略。 3. 建立 SoC 異質運算（CPU/GPU/ISP/NPU）系統模型，探索並驗證最佳化方案。 4. 提供效能分析報告，向決策團隊提出技術發展與架構演進方向。

1. 設計、開發和維護安全啟動（Secure Boot）系統和引導加載程序（Bootloader）。 2. 實施和優化安全措施，包括密鑰管理、數字簽名和加密技術。 3. 與硬體工程師緊密合作，以確保驅動程式與硬體設計的兼容性。 4. 整合應用端的技術要求，與應用開發團隊合作，確保 secure IP 驅動程式的順利整合。 5. 進行安全漏洞分析，並提出相應的緩解策略。

1. Familiar with DFT plan, methodology, implementation 2. Familiar with new DFT flow such as SSN, HSIO 3. Familar with STA, timing analysis

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification.

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification. * (If manager) Manage the design architecture team, focusing on both technological advancement and talent development.

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications • Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements • Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement • Location: Hsinchu, Taipei, Singapore, USA

0. 基本英文文書能力 1. Responsible for establishing and improving software engineering relevant systems and automation mechanism 2. Responsible for improving software configuration management systems 3. Responsible for improving release automation systems 4. Responsible for improving Linux build environment

1. 負責多媒體與周邊裝置的軟體及韌體開發（包含框架、驅動程式及功能開發）。 2. 執行客製化晶片功能驗證。 3. 進行系統效能優化及問題分析。

1. 參加 IEEE 802.11 會議, 協助發展新的 wi-fi 規格並與將需求設計架構實現在聯發科 wi-fi chip 內 2. 設計 Wi-Fi Platform 與 STA 系統架構, 協助開發改善 performance, QoS 需求

1.AI系統硬體規劃：系統規格與設計需求收集 2.AI系統硬體設計：負責設計和開發硬體系統架構，包括電路設計、元件評估與選擇、客製化元件規劃。 3. AI系統硬體驗證與測試：確認硬體系統正常運作，包含驗證與測試。 4. 跨組織合作：與IC design team、system team、SI/PI team與layout team等等合作，完成系統設計、製作與驗證。 5.客戶與相關廠商支援：包含技術文件撰寫、客戶參考設計支援、on site支援等等。

1. Implement and maintain device drivers, or firmware for high-speed interfaces, such as PCI Express, MIPI CSI-2, USB or UFS. 2. Develop FuSa and security software framework for high-speed interfaces to fulfill automotive requirements.

1. Work with design teams to do performance sign off in pre-silicon stage 2. ESL platform and simulation/emulation technology development. 3. Model development (includes behavior modeling/ cycle approximate modeling)

1.PCB 電路及layout 的設計及驗證 2. 客戶端平台之開發驗證

1. LCD Monitor IC相關的韌體開發 2. 影像處理相關應用與支援客戶產品開發 3. LCD Monitor周邊軟體tool開發

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

• Define GPU compiler software architecture and interfaces. • Development/implement GPU compiler pipeline, linking and various optimizations/transformations. • Collaborate with Driver team, HW team to implement new API & HW features. • Collaborate with Driver team, HW team to improve/tune performance & power consumption. • Execute & deliver to meet milestones/schedules. • Analyze and debug code generation issues. • Construct reliable & trustable relationships across teams internally & externally.

• Lead the DV effort of a high-end CPU project. • Manage, coach and guide DV engineers. Follow up status and keep up the schedule. • Architect and implement top-module testbenches and their components using UVM-based methods. • Lead the effort of building in-house BFMs to facilitate co-sim based module level verification. • Architect and implement formal verification based module level testbench. • Work with the design team to create testplans. Implement checkers/assertions/coverage check points. • Work with validation folks to improve design visibility

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

開發模擬以及PoC測試平台, 工作包括 - 實作分散式運算架構 - 利用Kubernetes container 管理架構 - 實作概念性驗證

Do you want to be part of a smart and passionate team of researchers, advancing artificial intelligence to the next level of end-user experience in their daily lives? MediaTek is seeking driven and brilliant young students to join our efforts by providing Internship placements. We are currently working to expand the frontiers of Deep Learning frameworks for Computer Vision and Natural Language Processing and we hope you can join us! The ideal candidate is open-minded, passionate about learning theory, and looks forward to both practical and challenging problems. • You will be working towards or recently have completed a PhD in a quantitative field such as Computer Science, Mathematics, Physics or Engineering. • You have a good knowledge of the foundations of Deep Learning and Neural Networks, including some experience with Machine Learning frameworks (Tensorflow, PyTorch, JAX) • You are a proficient scientific communicator. You are committed to your goals and working in a team. • You are eager to tackle the state of the art problems in the field. We want your ideas to shine! As a Deep Learning Researcher in our team, you will collaborate with our Researchers and with worldwide colleagues, stay up and above the state of the art, initiate with novel ideas, and develop them into algorithms and applications that make the real difference in everyday devices. You will also push your contribution by publishing at top-tier conferences, such as NeurIPS, ICML, ICLR, CVPR, ACL, ICRA, ACM.