交大專區

1.負責 ASIC Memory IP Driver 軟體開發與 IC驗證環境 2.熟悉軟/韌體、優化、IC驗證 及 除錯 等工作項目 3.執行 IC bring up 與韌體系統整合的工作

We are looking for experienced ML/DL candidates to join our team of PhD-level researchers and interns. The ideal candidate is open-minded, passionate about pushing learning theory, and keen on the opportunity to challenging convention. In a flexible and supportive environment, one of your major responsibilities is to push the state of the art of learning theory, to obtain insights beyond mythical theories as well as to apply the right solution to novel application areas such as AI-designed IC and General Intelligence Conversation. Furthermore, you shall actively engage with worldwide colleagues and academics to nurture and build a collaborative and effective R&D environment. We welcome all ML/DL backgrounds, including computer vision, speech and NLP, and robotics.

We are looking for aspiring ML/DL candidates to join our team of researchers. The ideal candidate is open-minded, passionate about pushing learning theory, and keen on the opportunity to challenging convention. Your ideas shall be based on sound mathematical justification, yet can lead to scalable and practical solutions. In a flexible and supportive environment, one of your major responsibilities is to push the state of the art of learning theory. Furthermore, through collaboration with worldwide colleagues, you will have the rare opportunity to apply advanced Deep Learning theories to novel application areas such as AI-designed IC and General Intelligence Conversation. We welcome all ML/DL backgrounds, including computer vision, speech and NLP, and robotics.

1. CoWoS和2.5D封裝技術開發 2. 3D封裝技術開發 3. CPC/CPO封裝技術開發 4. 封裝技術整合和NTO管理

* 資深SI/PI工程師 * 封裝/電路板 SI/PI設計與晶片開發於消費型產品, 車用以及企業級高效運算產品 * 記憶體以及高速Serdes SI/PI設計 * 高效能CPU/GPU/APU PI以及PDN設計 * 建立封裝/電路板的高速序號設計準則, PDN電氣規格, 以利產品進行

1. Package related structure stress analysis including warpage, material study. 2. Package and board level stress modeling for TCT, drop and vibration. 3. IC and package thermal analysis, modeling and characterization 4. Chip-Package-PCB thermal co-simulation and design. 5. System level thermal simulation 6. System level stress simulation

1. 屬於DE部門 2. 支援 WiFi/BT, 手機與 ARM computing等產品晶片開發計畫的FPGA與Emulation驗證工作與驗證技術開發 3. 主要為獨立貢獻者； 長期可依照潛力培養團隊領導能力，並有機會與全球科技產品的領導廠商有直接溝通合作的機會，可藉此培養個人與跨國的領導企業一起合作技術開發的能力。 4. 工作目標如下: a) 支援計畫功能與系統驗證與除錯 b) 規劃及協調驗證資源、項目及時程 c) 改善和加速multi-FPGA與Emulator工作流程 d) 增進FPGA與Emulator驗證效能 e) 研發SoC系統電路分析工具

. Familiar with ISO26262 safety software requirement breakdown for Cockpit and ADAS SoC, especially focus on SoC safety island . Customer Support: Provide technical support to customers and cross-departmental collaboration to ensure driver function development . Capable for the software architecture design and software safety analysis based on RTOS operating systems

職缺說明 我們是聯發科技IT MLOps平台團隊，致力於打造高效、可擴展的MLOps平台，提升企業AI模型開發、部署與運維自動化能力。團隊積極導入最新技術並持續學習成長，尋找具備MLOps平台架構設計與實踐經驗的菁英，一同推動公司AI數據驅動轉型。 歡迎對雲端/地端AI平台、機器學習自動化與大型系統架構有熱情的你加入我們！ 工作內容： 1 規劃並設計企業級MLOps平台架構，負責專案規劃、目標訂定、技術選型與落地執行。 2 與跨部門團隊AI合作，協助把商業問題拆解為可自動化實現的AI工作流，支撐AI模型端到端生命周期管理。 3 主導平台核心模塊建置：模型訓練/部署管線、CI/CD for ML、資料流通與版本控管、模型監控與資產管理等。 4 推動企業級MLOps標準化、流程自動化與最佳實踐，優化模型運營效能、穩定性及安全性。 5 參與平台持續優化與技術創新，導入新技術·新工具如Kubeflow、MLflow、Vertex AI等，提升平台功能。 6 協助建立團隊技術文化，分享MLOps相關知識、推動內部技術培訓與交流。

負責PCIe軟體開發，硬體功能驗證，以及量產support. 1. FPGA/SoC 驗證 2. Linux/RTOS/Window PCIe driver 開發 3. 軟硬體問題分析與解決 4. 系統規格討論 5. 客戶問題支援

We are looking for AI hardware architect/designer to join our team and play a pivotal role in designing, developing, and optimizing architecture of the neural processing unit (NPU). As an architect/designer, you will be responsible for creating innovative hardware and software solutions that meet the performance, scalability, and efficiency requirements of our advanced NPU environment. The ideal candidate will have a strong background in computer architecture, microarchitecture, and digital design, as well as experience with industry-standard tools and methodologies. You are expected to transform novel ideas into practical proposals for future NPU products, and vet the proposals via prototyping. Extensive knowledge in compiler and operating system is a plus. International travel may be required.

1. 數位電路設計 2. 多媒體電路設計 3. 系統整合

Fully accountable with the team to deliver highly competitive ARM based CPU IP. Implementation skill required ranged from RTL, synthesis, DFT, Floorplan, Placement, CTS, Routing, Timing Closure, and physical verification.

【職務概述】 我們正在尋找具前瞻視野與創新精神的工程領導者，加入生成式 AI 應用平台團隊，打造企業級 GenAI 平台，協助內部團隊快速開發 AI 應用與智能代理，推動數位轉型。您將領導團隊建構關鍵能力，包括 RAG 框架、多代理分析平台與 HyperAutomation 模組，並推進多代理協作、模型路由、LLMOps 標準化與負責任 AI 治理。 【主要職責】 策略與領導：帶領跨領域團隊，制定技術藍圖與 KPI，導入 RAG 2.0、知識圖譜、AI Agent 協作等技術。 平台研發：設計與維運 RAG 框架、多模態分析 Agent、AI 自動化模組，導入 MCP、LangGraph 等前沿技術，強化平台效能與治理。 利害關係人協作：作為技術策略夥伴，協助事業單位導入 GenAI，與資料、業務、安全團隊共創 AI 解決方案，推動開發者生態與負責任 AI 架構。

1. CPU/GPU STA, high-speed & low-voltage timing signoff/ timing closure 方法流程設計 2. STA 流程開發及應用 3. high-speed/low-voltage timing signoff criteria開發及應用 4. 針對project的STA/timing signoff問題進行分析及改善

1.數位電路設計 2.多媒體架構與電路設計 3.多媒體系統整合 1.Digital IC Design 2.Multimedia Architecture and Design 3.Multimedia System Integration

解讀客戶的網絡安全需求 從網絡安全需求中推導出功能和安全概念 制定和審查安全系統架構 與 IP 團隊和客戶溝通和協調安全設計 執行系統安全分析（例如：TARA）

1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit.

We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

1. 開發用於模擬手機/平板/車用SOC功率消耗的平台 2. 協助IP, SOC與軟體團隊，維護用於功耗分析的資料庫，開發相關工具以輔助跨團隊的資訊整合 3. 優化系統效能，輔佐系統功耗相關決策的進行