交大專區

- Optimize GPU performance, area/power for representative workloads (graphics and compute) from the perspectives of memory sub-system, low-power design/policy and implementation strategy. - System modeling framework to simulate hardware with different accuracy/throughput tradeoffs at different stages of the design; supervise Performance/Power/Area investigation/validation and facilitate architecture/design decisions

Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.

- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. - Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. - Create and execute verification test plans, focusing on functional coverage. - Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. - Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. - Support performance verification, emulation, data collection, debugging, and PPA improvements. - Conduct formal verification.

Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

About the Role: Bring your GPU driver expertise and work closely with our Architecture and Micro-architecture teams. In this role, you will contribute across the GPU software stack and help extract maximum performance from the silicon while supporting the development of our next-generation GPU designs. This is not a siloed driver role. You will have opportunities to work across industry-standard graphics and compute APIs, kernel-mode drivers, GPU firmware, performance optimization, and hardware/software integration. What You‘ll Do — The Full Stack: • API Layer: Develop, debug, and optimize features for industry-standard APIs including Vulkan, DirectX, OpenGL ES, and OpenCL. • Kernel & Firmware: Work on kernel-mode drivers and GPU firmware to improve hardware control, stability, scheduling, memory management, and execution efficiency. • Performance: Analyze and optimize bottlenecks across the stack, including driver overhead, memory bandwidth, GPU scheduling, compute throughput, and power/performance tradeoffs. • Cross-Team Collaboration: Work closely with Architecture, Micro-architecture, Compiler, and GPU Model teams to validate GPU behavior, debug complex issues, and improve software/hardware interaction. • System-Level Debugging: Investigate issues across user-mode drivers, kernel-mode drivers, firmware, and hardware models to improve stability, correctness, and performance. Why This Role? • No Silos: You are not restricted to only one layer of the stack. You will have the opportunity to work across APIs, drivers, firmware, and performance. • Hardware-Software Impact: Your work will help the software stack fully utilize GPU hardware capabilities. • Next-Gen GPU Exposure: You will collaborate with architecture, compiler, and modeling teams on technologies that shape future GPU products. Ready to work across the entire GPU stack? Apply today.

Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting

1. CPU system design and performance analysis 2. AMBA System bus architecture and integration 3. IP and system design and verification

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis 2. Basic knowledge of analog design 3. Mixed signal design experience is a plus. 4. SoC architecture exploration and performance analysis experience is plus. 5. Post-silicon mass production experience ((Ex: DFT, CP, FT)) is a plus. 1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 2 . 具類比IC設計的基本知識 3. 混和訊號IC設計經驗是加分項 4 . 系統架構分析經驗是加分項 5 . 具IC量產相關經驗(Ex: DFT, CP, FT)是加分項

We are looking for talented engineers to join our GPU Architecture team. In this role, you will be at the forefront of defining the next generation of mobile high-performance GPUs. You will be responsible for developing a C++ based model, which serves as the primary tool for architectural exploration, bottleneck analysis, and performance projection before silicon availability. Whether you are a fresh graduate with a strong passion for computer architecture or a seasoned veteran in performance modeling, we invite you to help us push the boundaries of graphics rendering and compute efficiency.

職位與職責： 1. 定義 GPU 編譯器軟體架構及介面。 2. 開發/實作 GPU 編譯器流水線、連結以及各種最佳化/轉換。 3. 與驅動程式團隊及硬體團隊合作，實作新的 API 與硬體功能。 4. 與驅動程式團隊及硬體團隊合作，改善/調整效能與功耗。 5. 執行並交付專案，以達成里程碑與進度要求。 6. 分析並除錯程式碼生成相關問題。 7. 分析並影響未來 GPU 架構的設計。 8. 與內部及外部團隊建立可靠且值得信賴的合作關係。

1. 開發並整合 AI 智能體框架 2. 開發並整合軟體工程系統，以優化軟體開發生命週期 3. 蒐集與分析系統需求及系統設計 4. 支援緊急系統功能或效能問題處理

您將擔任面向關鍵客戶的 AI 架構負責人（Architecture Owner）與主要窗口（Directly Responsible Individual），與客戶及內部研發/產品/平台團隊密切協作，推動 AI 相關需求定義、系統架構設計、效能與品質目標落地、以及問題閉環。此角色需要同時具備深度技術能力與跨組織推動能力，能將客戶需求轉化為可交付的技術方案與量產路徑。

1. Make test pattern plan to cover system bring-up for MP (CP/FT, system test, DVT, HQA, correlation, DPPM reduction) 2. Debug post-silicon issue to identify design weakness and solution finding 3. Correct post-silcion measurement vs. pre-silicon simulaiton, including process, performance, power.

1. 負責CP/FT/SLT/Burn-in/Socket 測試配件開發與驗證 2. 先進封裝測試配件新技術新需求開並導入量產 3. 測試配件供應商管理

1. 系統開發高速訊號測試計畫, 環境, 驗證與除錯. 2. 研究分析比較與效能評比. 3. 制定系統驗證機制與強化重複性測試環境 4. 負責在計畫時程規劃內完成系統驗證與除錯. 5.全球客戶專案技術支持

1. USB3 Controller Maintainess/Development 2. Short term =＞ Handle the USB3 Controller for different projects and adding new features. Long term =＞ Co-work with USB4 team to co-develop the next gen USB4 controller

1. USB3 Controller Maintainess/Development 2. Leading the new USB3 design team 3. Short term =＞ Handle the USB3 Controller for different projects and adding new features. Long term =＞ Co-work with USB4 team to co-develop the next gen USB4 controller

1. 角色定位：位於 PMO 核心樞紐，推動內部數位工具演進，提升跨團隊協作與營運效率 2. 主要任務：開發/維護專案管理工具、流程自動化、AI（生成式 AI）整合與數據儀表板 3. 工作比例：全端/AI 70％｜專案協作 20％｜流程/文件 10％

CPU IC 產品發展, 產品量產管理與良率改善, 除錯與問題的解決

我們正在尋找充滿熱情的產品安全工程師或研究員 (Offensive Security)，加入我們的團隊，共同鞏固我們的產品安全。這個職位將為您提供豐富的學習和成長機會，讓您在快速發展的資安領域中脫穎而出。 [工作內容] 1. 安全威脅建模: 對系統安全進行威脅建模，提出安全設計改善建議，並完善安全設計規範。 2. 漏洞分析測試: 對軟體安全進行漏洞分析、安全代碼審查，以及進行模糊/滲透測試。 3. 滲透測試開發: 發展用於漏洞發現的滲透測試方法、腳本或測試工具。 4. 前沿攻擊研究: 研究最先進的攻擊/駭客方法及趨勢，以精進各項安全測試工具及手法。 實際工作內容和範圍將根據所參與的任務而定。 [工作地點] 台北/新竹 [學習成長機會] 1. 技術多樣性: 有機會學習和接觸各式各樣的產品核心技術，擴展您的技術知識面。 2. 實戰的經驗: 與世界一流的資安研究人員合作進行安全性審查，獲得寶貴的實戰經驗。 3. 國際的視野: 參與國際資安會議，了解最新的安全趨勢和技術，提升您的專業知識。 4. 跨領域合作: 與不同技術領域的專家合作，提升您的跨領域協作能力。 加入我們，您將有機會在一個充滿挑戰和機遇的環境中成長，並為全球的產品安全做出貢獻。如果您對資安充滿熱情，並希望在這個領域中不斷進步，我們誠摯邀請您加入我們的團隊!