交大專區

生醫訊號感測類比電路設計, 系統設計及驗證

類比混合信號電路設計

• You will work as part of analog project management team and work closely with SoC Integration teams responsible for enabling on-time silicon to meet aggressive product schedules. • Multi-task skills will be key to lead several tasks of project at a time. • Track and drive resolution of technical issues between multi-functional teams including Design, Verification, Validation, Process Technology, Packaging, Quality and Reliability, System Hardware and Application. • Convert data into a clear story to communicate to partners and organizations at all levels. • Pull together regular project status presentations for executive leadership review. • Identify risks, develop mitigation strategies and facilitate conflict resolution. • Collaborate with software/hardware teams for silicon validation of analog IPs • Deliver highly focused and detailed issue reporting, bug tracking and communication of risks and status

1. 針對電視螢幕顯示器開發即時視訊處理演算法 2. 針對電視顯示器SoC開發畫質演算法之韌體. 3. 與硬體設計工程師共同實現演算法於IC. 4. 與客戶共同開發客製化畫質演算法

1. 規劃與研究 Windows/ARM/UEFI 安全技術與功能　 2. 實作Windows/ARM/UEFI 安全技術與功能

1. 制定與優化專案開發流程 , 偕同軟體工程單位達成專案目標 2. 管理與稽核專案流程執行 3. 管理與分析專案執行資料 4. 擔任跨團隊 taskforce lead，帶領團隊解決特定議題

1. Utilize analytical, statistical and programming skills to collect, analyze and interpret large data sets; 2. Support operations technology program manager to fulfill the analytics program’s target and output 3. Collaborate with program managers, leaders and stakeholders to identify and optimize the information infrastructure and management system

工作地點: 新竹/台北/美國 1. 開發安卓服務 和 linux 守護進程 以理解使用者和應用程式行為 2. 開發Linux驅動/eBPF，收集硬體統計和相關操作條件 3. 在行動裝置上開發具有高性能和低開銷的行動數據儲存和分析平臺 4. 優化安卓設備的性能/功率/熱/遊戲/多媒體 體驗 5. 為下一代產品提供平衡成本和競爭力的設計指導

1. System design and performance evaluation for advanced wireless communication systems 2. B5G standardization-related activity 3. Log analysis and p

1. 提出系統層次的軟硬體競爭分析 2. 分析系統架構: 從系統效能/功耗/散熱面及跨不同軟/硬體模組 3. 研發次世代系統架構: 提出有競爭力且系統最佳化軟體演算法與軟硬體架構設計最佳方案 1. Propose competitive analysis of system-level SW/HW and applications 2. Research systemic issues from performance/power/thermal analysis cross software and hardware modules 3. Propose competitive analysis, near-optimal software algorithm, and/or hardware suggestion for next-generation system architecture

CPU 能耗管理架構及調教 Power management architect and tuning on Android OS or RTOS

1. Build-up methodology for SoC system-level modeling and emulation platform (ex. Zebu, PXP) 2. Analyze GPU benchmarks and critical game applications, identify performance bottlenecks from computing system level and provide HW/SW optimizations 3. Explore the best-fit computing system architecture for next generation IP and SoC

System software of AFE design, modem IDC, TA-SAR and BT COEX

• Leading Bluetooth protocol stack software development • Leading customer requirement implement and support

• Review security architecture and design • Security feature development • Make connectivity IP meet MediaTek Security baseline & customer security requirement

Work location: Chupei/Taipei UWB architecture design for mobile market

Work location: Chupei/Taipei WiFi MAC/baseband architecture design to fulfill wearable/IOT product requirement

1. Work for Protocol verification in System Verification, to communicate with teams and co-work with modem R&D in multiple-sites in the world 2. Drive Inter-operability test Projects, for Planning, Preparation and Test execution in Japan operators Lab and Field Test. 3. Analysis and report modem protocol related issues, to collaborate with team members in System Verification and modem R&D. 4. Track modem related issues and contribute the fast correction delivery. 5. Provide technical support, to lead prompt solution to internal/external customers

Power management IC design Audio IC design Data converter IC design high speed serdes IC design

- Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power. - Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. - Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. - DFT insertion, ATPG and gate-level simulation - Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). - Interact with Physical Design Engineers and provide them with timing/congestion feedback.