交大專區

•Architecture definition and analysis •SOC performance modeling, studies and analysis •Power and Performance trade-off analysis •Research on performance/power/area •Chip partition analysis

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 3.執行或協助功秏量測, 與power model預估的功秏做校正 4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗

Optimize GPU performance, area/power for representative workloads (graphics and compute) from the perspectives of memory sub-system, low-power design/policy and implementation strategy. System modeling framework to simulate hardware with different accuracy/throughput tradeoffs at different stages of the design; supervise Performance/Power/Area investigation/validation and facilitate architecture/design decisions;

1. 802.3 Ethernet PHY 應用整合設計,IC功能驗證與系統效能改善 2. 與硬體/演算法/軟體同仁合作開發晶片從雛型設計到量產 3. 與軟體同仁共同設計自動化驗證高速介面並除錯,e.g. USB, PCIe, xGMII, Ethernet, MIPI 4. 支持客戶應用及IP導入

1. 架構和數位電路設計 2. RTL實做和驗證 3. SoC chip整合和RTL到gate level實現, 包含timing分析跟量產測試 4. 設計方法和整合流程改善

1. SOC 整合工作, 從RTL到GDS 2. Synthesis / Timing closure / DFT / LEC / QC 3. 參與實體設計專案, floorplan/CTS/PnR 4. 使用Perl/Tcl 優化工作流程

•我們在一個節奏快且敏捷的工作環境, 聚焦長期目標, 動手解決真正問題, 將 AI 落地在真實世界, 並發表論文在頂級會議與期刊. 歡迎加入我們. •此職位將協助部門AI專案之推廣相關事宜, 包含但不限於服務部屬與測試, 模型狀況監測. •This is a technical role, and it requires a high willingness to learn state-of-the-art AI techniques and a skill to apply AI techniques to business applications/processes. This job opening encompasses a wide range of end-to-end ML pipeline activities, including framing AI problems, data collection/preprocess/exploration, model development/evaluation, model deployment/monitor. Our major responsibilities include (1) landing AI in real world (2) publication at top conference/journal (DAC, IEEE/TCAD, ICLR, ICML…). Here, you will be working in a fast-paced and agile environment which needs a mindset of a startup. Together with worldwide colleagues you will deliver everything from state-of-the-art algorithms to quicker value proving solutions. •This position will assist in the promotion of the departments‘s AI project, including but not limited to service deployment, and model status monitoring.

1. 研究IP開發測試計畫, 環境, 驗證與除錯. 2. IP開發驗證. 3. 研究分析IP比較與效能評比. 4. 制定IP驗證機制與強化重複性測試環境以提供給產品使用. 5. 負責在計畫時程規劃內完成IP驗證與除錯.

人工處理器系統架構及RTL設計。 系統架構設計包含效能、功耗、D頻寬、以及面積分析。 並須負擔RTL實做。

We are looking for Machine Learning/Deep Learning engineers. This is a technical role, and it requires a high willingness to learn state-of-the-art AI techniques and a skill to apply AI techniques to business applications/processes. This job opening encompasses a wide range of end-to-end ML pipeline activities, including framing AI problems, data collection/preprocess/exploration, model development/evaluation, model deployment/monitor. Our major responsibilities includes (1) landing AI in real world (2) publication at top conference/journal (NIPS, CVPR, ICLR, ICML…). Here, you will be working in a fast-paced and agile environment which needs a mindset of a startup. Together with worldwide colleagues you will deliver everything from state-of-the-art algorithms to quicker value proving solutions.

1. 負責建立與改善軟體開發流程相關的資訊系統及自動化機制 2. 負責建置與維護〝持續整合(CI)〝、〝持續交付(CD)〝相關資訊系統與服務 3．新技術或軟體開發方法調研與導入，例如: AI, RPA等

1. 與軟體工程師合作優化系統性能、能效及記憶體管理。 2. 分解AI系統性能及功耗並進行瓶頸分析 3. 與軟體工程師和算法開發人員合作以整合出符合客戶需求之AI軟體架構 4. 瞭解系統權衡, 提出下一代架構之改進建議

高速與低功耗GPU實作(P&R), Power/Performance/Area/Schedule改善及FLOW開發 The candidate who fills this position will work closely with GPU hardware designer, IP and flow teams to improve GPU power/performance/area/schedule/yield. Candidate is responsible for all aspects of physical design and implementation of large GPUs which are targeted at the DTV, smart phone markets. Responsibilities include GPU hierarchical physical implementation/coordination (floor plan, block assembly, power/clock distribution, timing closure, power, IR, noise analysis and back-end verification). Also responsible for flow development with focus on improving GPU development schedule, chip cost, chip power, chip performance, yield, and development resources.

1. 數位電路開發設計與整合 2. IP與系統層級驗證，包含FPGA和實際晶片 3. 數位流程執行與優化 4. IP文件與功能維護

[職缺一] 1.IC 整合 2.IC設計整合流程改善 3. 數位IP設計/IC整合/系統驗證 [職缺二] 1.執行晶片sign-off流程 2.發展降低晶片功耗流程 3.整體晶片的靜態時序分析與收斂

1. 無線網通系統, 數位設計 2. Micro Processor, 系統架構, low power/效能分析 3. SOC 整合/驗證 1. Wireless connecitivity system (GPS or BT or WiFi or FM or NFC or 60G) baseband or MAC design 2. uP/DSP system/peripheral architecture and digital circuit design 3. SoC chip integration / Verification

多核心處理器系統驗證工程師: -Constrain random verification for 處理器和外圍設計電路 -以Coverage driven的低功耗驗證 -基於硬體電路架構的，Formal 靜態驗證

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow

Responsible for digital design verification of power management IC 1. Define verification plan 2. Create testbench and verify design functionality 3. Develop verification environment 4. Explore DV methodology

(1) Verification Planning 1.1 DSP platform module and/or system design 1.2 5G/6G modem module and/or system design (2) Testbench Build-Up 1.1 Constrained random verification by SystemVerilog/UVM usage 1.2 Reference modeling 1.3 Assertion check 1.4 Coverage closure (3) Coordination with Algorithm/Digital design/Software teams