交大專區

1.顯示器/Branch 產品driver研發 2.Driver porting 與改善driver效能 3.負責Display Port driver開法跟問題排除 4.分析相容性問題

1. Perform PMIC/SerDes circuit verification using advanced verification methodologies 2. Analog/Mixed-Signal circuit verification methodology / flow development. 3. Analog/Mixed-Signal circuit behavior model(Verilog-A/Verilog/SV) creation

徵求具創意且有經驗之XR顯示系統軟體工程師, 尤其針對XR Warping算法之開發整合及優化. - 需與IC設計團隊共同設計下一代IC. - 需與軟體團隊密切合作改良軟體架構以符合產品需求

1. WiFi/BT 電路系統分析、IC驗證除錯、公板製作、數據蒐集及分析 2. PCB公版設計, 除錯 3. EMI 防治對策 4. 高速數位介面應用及除錯 5. 客戶支持

1. 先進製程(＜N5)的可測試電路實作流程開發 2. 先進製程(N4/N3)可測試錯誤模型的研究與實作 3. 針對超高速與超低壓電路錯誤模型的研究與實作 4. 量產測試dppm分析與除錯, 測試效率的改善 5. 系統軟硬體測試的分析與除錯

1. 開發公司手機/平板所需的Clock與電源管理IC 2. 負責系統規格的制定,功能驗證與系統效能改善 3. 與硬體/軟體/演算法同仁合作開發晶片從雛型設計到量產 4. 產出參考韌體給不同專案整合並量產 5. 該職缺可任職於新竹或台北

CPU Physical design, including 1. floorplan, P&R, CTS and timing closure 2. Physical verification

- Co-work w/ foundry/EDA vendors to define best PD imp recipes - Explore EDA tool new features and introduce to project team - Define proper FOM to project DTCO opportunities - Optimize PG structure for best resource and IR/EM concerns, including pillar types, via stacking layers - Help project team revise scripts, provide guidelines/checkers to check PD quality and feedback potential issues - Build physical-aware timing diagnosis utilities

1. 電源管理晶片與低功耗系統設計 2. 混合信號積體電路: 電源控制, 數位控制震盪器, AUXADC, SerDes 應用等 3. 數位電路設計與晶片整合 (frontend/backend integration)

1. PMIC/SerDes 電路驗證 2. 類比電路驗證方法流程開發 3. Serdes/類比/RF電路之IR/EM 分析 4. 類比電路 Verilog-A 行為模型開發 5. 晶片-封裝 (WLCSP/CoWoS/3DIC/InFO 3D.)IR/EM 協同分析流程開發 6. 類比/射頻 CPM 模型化

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

1. 先進製程技術製程開發 2. 先進封裝技術開發

• Leading 802.11BE & wearable software structure & algorithm development • Leading customer requirement implement and support

1. 類比IC設計 2. 電源管理IC或ADC/PLL/Serdes類比電路整合及下線

In this role, you will be a member of the System-on-Chip (SoC) platform modeling team, working with architecture, silicon and software engineering teams to shape the architecture of MediaTek‘s future SoCs. The position calls for independent performance modeling and analysis, documentation, and collaboration with teams across MediaTek. We are looking for highly motivated, hands-on individuals who are passionate about performance modeling of sophisticated SoC features in C++/Python to demonstrate their value and impact. Major Responsibilities: •Responsible for evaluating and improving the SoC performance and efficiency •Developing C++ performance models (C-model) of SoC architectural solutions and features. •Developing tests and microbenchmarks to represent the use cases to run on the model •Gathering and analyzing simulated performance data to evaluate architectural design alternatives under various SoC workloads and benchmarks. •Correlating performance of the SoC RTL infrastruct

1. Windows on ARM system analysis: find out critical path of platform performance/energy and workload behavior 2. Plan and develop scenario-base abstract models of Windows for power and performance estimation

1. 主要處理28nm及以下之先進製程 2. 負責後段APR flow 3. 需參與團隊, 合作完成專案 4. 需撰寫程式

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform IR signoff and Chip-Package Co-Design 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

•Architecture definition and analysis •SOC performance modeling, studies and analysis •Power and Performance trade-off analysis •Research on performance/power/area •Chip partition analysis

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 3.執行或協助功秏量測, 與power model預估的功秏做校正 4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗