交大專區

Responsible for digital design verification of power management IC 1. Define verification plan 2. Create testbench and verify design functionality 3. Develop verification environment 4. Explore DV methodology

1. DSP處理器和相對應的周邊IP驗證環境開發 2. 從module, IP 到system的功能驗證及自動化環境 3. 設計測試pattern以對低耗電及效能做分析 4. Post-silicon 除錯 及 耗電/效能correlation

1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核

We are heavily recruiting talents and professionals in DV, EDA, and AI/ML fields to join our force to conquer new heights in chip complexity! As one of the world’s top IC design companies, MediaTek is constantly pushing the capabilities of chips to the limits. Our newest SoCs and ASICs are wildly sophisticated, packed with industry-leading technologies built by thousands of chip designers. With great design power comes great verification responsibilities. Our team, as a part of the verification force, has put major efforts into creating innovative and robust strategies to fulfill these responsibilities. To ensure high design quality for first silicon success, we have implemented a complete suite of functional and low-power test plans and benches across all design scopes, from IPs to SoC integrations. Furthermore, we have been collaborating with EDA tool providers and academic institutions on leveraging new verification technologies, including emulation, AI tuning, and formal methods, many of which have improved the traditional workflows by orders of magnitude. We also keep challenging ourselves to develop in-house verification tools and platforms to accelerate test regressions and track verification progress more efficiently. All these efforts ultimately lead to our success in delivering high-quality chips over the years.

1. 高速SerDes IP開發 2. 數位電路設計與晶片整合 3. 訊號處理與通訊演算法實現

(1) Verification Planning 1.1 DSP platform module and/or system design 1.2 5G/6G modem module and/or system design (2) Testbench Build-Up 1.1 Constrained random verification by SystemVerilog/UVM usage 1.2 Reference modeling 1.3 Assertion check 1.4 Coverage closure (3) Coordination with Algorithm/Digital design/Software teams

1) 開發針對本公司晶片設計所使用的EDA工具,工作內容包含:需求分析,演算法設計,資料處裡,與使用者介面設計 2) 推廣與嵌入新的流程到未來開案的晶片,目標是提升晶片開發的效率與品質 3) 透過設計演算法或以AI技術來定義與解決IC設計流程遇到的難題

1. 記憶體電路設計與驗證 2. 記憶體編譯器平台開發

電磁干擾設計工程師主要負責射頻與類比電路信號完整性 (RF/Analog signal integrity) 、電磁干擾 (EMI/EMC) 分析與及封裝天線 (Antenna-in-Package) 設計。藉由開發”晶片+封裝+印刷電路板”共設計流程來解決高整合數位/類比電路的干擾問題，以提供客戶高性價比的 RFSOC/RFSIP 無線通訊 (cellular 4G/5G) 及無線連結 (WiFi, BT, GPS, FM radios) 產品。 1. 射頻與類比電路信號完整性分析與設計 2. 射頻系統單晶片 (RFSOC/RFSIP) 電磁干擾分析與設計 3. 封裝天線設計與驗證 4. “電路+封裝+印刷板” 共模擬平台開發與驗證 5. Design Guide 的撰寫與推廣

高效能/低成本/低功耗/高效率，具延展性的階層式Smartphone SOC on chip bus 構架設計

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis and post silicon debugging 2. Low power analysis, including pre-silicon power model creation and big data analysis 3. SoC architecture exploration and performance analysis experience is plus

擔任 數位IC設計團隊內的 計劃開發與控管工作 (Modem IP project lead) 1.規劃計劃開發的時程 與 檢視人力需求 2.追蹤RTL開發/驗證進度, 前/後段整合開發進度, 與APR狀況, 並控制品質 3.定期公告 各計畫狀態 4.與客戶溝通 開發團隊的 不良晶片分析狀況 Handling digital design team project development/ control jobs (Modem IP project lead) 1.Defining project schedule and resource 2.Tracking RTL development/verification status, front-end/back-end integration status and APR status, and control quality 3.Providing regular project status reports 4.Communication with client for fail chip analysis stoats

高速與低功耗GPU實作(P&R), Power/Performance/Area/Schedule改善及FLOW開發 The candidate who fills this position will work closely with GPU hardware designer, IP and flow teams to improve GPU power/performance/area/schedule/yield. Candidate is responsible for all aspects of physical design and implementation of large GPUs which are targeted at the DTV, smart phone markets. Responsibilities include GPU hierarchical physical implementation/coordination (floor plan, block assembly, power/clock distribution, timing closure, power, IR, noise analysis and back-end verification). Also responsible for flow development with focus on improving GPU development schedule, chip cost, chip power, chip performance, yield, and development resources.

【職缺一】APR實體設計工程師 1. Working on advanced node design methodology, PD execution and sign-off 2. Develop advance clock tree structure 3. Able to handle complex APR with 500+ hardmacros 4. Project analysis in early stage 【職缺二】超大型SoC實體設計工程師 1. executing ultra-large scale SoC hierarchical physical design, in TOP level or GHz complex block level 2. Full experienced PD who can manage/coordinate other PDs‘ various number of hierarchical blocks 3. Flow development experience is a plus, to consolidate ultra-large scale SoC methodologies

CPU Physical design, including 1. floorplan, P&R, CTS and timing closure 2. Physical verification

對數位電路設計有熱忱者，負責 IP 開發, 整合與偵錯

1. 數位電路開發設計與整合 2. IP與系統層級驗證，包含FPGA和實際晶片 3. 數位流程執行與優化 4. IP文件與功能維護

• 參與3GPP RAN4會議，包括可能的線上或線下討論，以及協助撰寫會議技術文稿 • 檢驗內部及外部標準提案的有效性，透過鏈路級模擬或系統級模擬來撰寫技術文稿 • 於鏈路級模擬或系統級模擬程試中開發新的模組來支援最新3GPP標準的功能 • 參與內部或外部會議，提供想法創意，以及所需之效能評估

Baseband手機系統應用與電源規格制定, 包含modem, PMIC and AP.

- Co-work w/ foundry/EDA vendors to define best PD imp recipes - Explore EDA tool new features and introduce to project team - Define proper FOM to project DTCO opportunities - Optimize PG structure for best resource and IR/EM concerns, including pillar types, via stacking layers - Help project team revise scripts, provide guidelines/checkers to check PD quality and feedback potential issues - Build physical-aware timing diagnosis utilities