交大專區

• 負責 Web 前端元件開發並完成交付 • 與 UI/UX designer 合作，制定使用者介面 • 與 PM 確認系統需求與操作流程，以實作商業邏輯 • 與 Backend engineer 合作，進行 API 整合與開發 • 頁面效能調校、持續更新前端元件架構

協助管理公司軟體資產與用量規劃，協助供應商幫忙除錯與進行教育訓練，教學文件撰寫以及進行簡易用戶問題排除

1. 主要處理28nm及以下之先進製程 2. 負責後段APR flow 3. 需參與團隊, 合作完成專案 4. 需撰寫程式

1. SOC 整合工作, 從RTL到GDS 2. Synthesis / Timing closure / DFT / LEC / QC 3. 參與實體設計專案, floorplan/CTS/PnR 4. 使用Perl/Tcl 優化工作流程

1. Perform PMIC/SerDes circuit verification using advanced verification methodologies 2. Analog/Mixed-Signal circuit verification methodology / flow development. 3. Analog/Mixed-Signal circuit behavior model(Verilog-A/Verilog/SV) creation

徵求具創意且有經驗之XR顯示系統軟體工程師, 尤其針對XR Warping算法之開發整合及優化. - 需與IC設計團隊共同設計下一代IC. - 需與軟體團隊密切合作改良軟體架構以符合產品需求

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform IR signoff and Chip-Package Co-Design 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

•Architecture definition and analysis •SOC performance modeling, studies and analysis •Power and Performance trade-off analysis •Research on performance/power/area •Chip partition analysis

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 3.執行或協助功秏量測, 與power model預估的功秏做校正 4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗

1. 研究IP開發測試計畫, 環境, 驗證與除錯. 2. IP開發驗證. 3. 研究分析IP比較與效能評比. 4. 制定IP驗證機制與強化重複性測試環境以提供給產品使用. 5. 負責在計畫時程規劃內完成IP驗證與除錯.

1. 與軟體工程師合作優化系統性能、能效及記憶體管理。 2. 分解AI系統性能及功耗並進行瓶頸分析 3. 與軟體工程師和算法開發人員合作以整合出符合客戶需求之AI軟體架構 4. 瞭解系統權衡, 提出下一代架構之改進建議

•我們在一個節奏快且敏捷的工作環境, 聚焦長期目標, 動手解決真正問題, 將 AI 落地在真實世界, 並發表論文在頂級會議與期刊. 歡迎加入我們. •此職位將協助部門AI專案研發與實驗, 包含但不限於問題定義, 價值闡述, 實驗規劃, 模型開發. •This is a technical role, and it requires a high willingness to learn state-of-the-art AI techniques and a skill to apply AI techniques to business applications/processes. This job opening encompasses a wide range of end-to-end ML pipeline activities, including framing AI problems, data collection/preprocess/exploration, model development/evaluation, model deployment/monitor. Our major responsibilities include (1) landing AI in real world (2) publication at top conference/journal (DAC, IEEE/TCAD, ICLR, ICML…). Here, you will be working in a fast-paced and agile environment which needs a mindset of a startup. Together with worldwide colleagues you will deliver everything from state-of-the-art algorithms to quicker value proving solutions. •This position will assist the department in AI project development and experimentation, including but not limited to problem definition, value elaboration, experiment planning, and model development.

1. WiFi/BT 電路系統分析、IC驗證除錯、公板製作、數據蒐集及分析 2. PCB公版設計, 除錯 3. EMI 防治對策 4. 高速數位介面應用及除錯 5. 客戶支持

1. 先進製程(＜N5)的可測試電路實作流程開發 2. 先進製程(N4/N3)可測試錯誤模型的研究與實作 3. 針對超高速與超低壓電路錯誤模型的研究與實作 4. 量產測試dppm分析與除錯, 測試效率的改善 5. 系統軟硬體測試的分析與除錯

Optimize GPU performance, area/power for representative workloads (graphics and compute) from the perspectives of memory sub-system, low-power design/policy and implementation strategy. System modeling framework to simulate hardware with different accuracy/throughput tradeoffs at different stages of the design; supervise Performance/Power/Area investigation/validation and facilitate architecture/design decisions;

1. 開發公司手機/平板所需的Clock與電源管理IC 2. 負責系統規格的制定,功能驗證與系統效能改善 3. 與硬體/軟體/演算法同仁合作開發晶片從雛型設計到量產 4. 產出參考韌體給不同專案整合並量產 5. 該職缺可任職於新竹或台北

1. 802.3 Ethernet PHY 應用整合設計,IC功能驗證與系統效能改善 2. 與硬體/演算法/軟體同仁合作開發晶片從雛型設計到量產 3. 與軟體同仁共同設計自動化驗證高速介面並除錯,e.g. USB, PCIe, xGMII, Ethernet, MIPI 4. 支持客戶應用及IP導入

1. 先進製程技術製程開發 2. 先進封裝技術開發

• 帶領與整合類比IP團隊與技術, 開發新的SOC或ASIC產品 • You will work as part of analog project management team and work closely with SoC Integration teams responsible for enabling on-time silicon to meet product schedules. • Multi-task skills will be key to lead several tasks of project at a time. • Track and drive resolution of technical issues between multi-functional teams including Design, Verification, Validation, Process Technology, Packaging, Quality and Reliability, System Hardware and Application. • Convert data into a clear story to communicate to partners and organizations at all levels. • Pull together regular project status presentations for executive leadership review. • Identify risks, develop mitigation strategies and facilitate conflict resolution. • Collaborate with software/hardware teams for silicon validation of analog IPs • Deliver highly focused and detailed issue reporting, bug tracking and communication of risks and status

We are looking for Machine Learning/Deep Learning engineers. This is a technical role, and it requires a high willingness to learn state-of-the-art AI techniques and a skill to apply AI techniques to business applications/processes. This job opening encompasses a wide range of end-to-end ML pipeline activities, including framing AI problems, data collection/preprocess/exploration, model development/evaluation, model deployment/monitor. Our major responsibilities includes (1) landing AI in real world (2) publication at top conference/journal (NIPS, CVPR, ICLR, ICML…). Here, you will be working in a fast-paced and agile environment which needs a mindset of a startup. Together with worldwide colleagues you will deliver everything from state-of-the-art algorithms to quicker value proving solutions.