交大專區

1. 熟悉ISP和相機架構流程，以開發ISP調適算法 2. ISP調適算法自動化開發 1. Familiar with ISP & whole camera system, and developing ISP tuning methodology 2. Tuning methodology automation development

System software of AFE design, modem IDC, TA-SAR and BT COEX

• Leading Bluetooth protocol stack software development • Leading customer requirement implement and support

• Review security architecture and design • Security feature development • Make connectivity IP meet MediaTek Security baseline & customer security requirement

Work location: Chupei/Taipei UWB architecture design for mobile market

• Leading 802.11BE & wearable software structure & algorithm development • Leading customer requirement implement and support

Work location: Chupei/Taipei WiFi MAC/baseband architecture design to fulfill wearable/IOT product requirement

• 專注於使用 Modern Web 技術開發提升公司各部門團隊生產力 • 擁抱產品及數據思維，以數據驅動產品功能之開發決策 • 以使用者故事 (user story) 作為開發依據，採用敏捷式開發 (Agile development) 快速迭代產品 • 重視團隊成員能力成長及團隊向心力，每月由不同成員定期做軟硬技術分享，進而達成組織目標 • 自動化測試部署確保軟體品質及提升工作效率減少時間浪費 工作內容：維護公司內部系統

1. 開發, 優化與維護 4G/5G Modem 自動化整合測試平台, CI Flow 等. 2. 開發, 優化與維護 4G/5G Modem Simulator 3. 開發, 優化與維護 4G/5G Modem 研發流程與驗證平台的 Tool Chain

-建立通訊系統模擬平台及利用模擬實驗驗證系統設計 -確保通訊系統模擬平台符合3GPP標準規範以及與基站及儀器商的一致性 -修改通訊系統模擬平台以符合實際軟硬體實作設計 - Model system level behavior and validate the design by simulations - Ensure the system simulator to comply with 3GPP spec and align with infra and machine vendors - Modify the system simulator to match the practical HW/SW partition for design verification

分析及優化手機 5G TestBed 平台的效能，包括以下項目 1. 整合與移植不同 Linux 平台 (Ex. Ubuntu, Cent, RedHat, ...) 2. 整合與應用 Intel/AMD CPU Accelerator API (Ex. Intel Core i9 9/10/12th AVX/TBB/MKL; AMD...) 3. 分析與調校系統整體效能 (Ex. Linux Kernel, Process, Thread, Peripheral(Ethernet/PCIe/...) Driver, ...)

1. Work for Protocol verification in System Verification, to communicate with teams and co-work with modem R&D in multiple-sites in the world 2. Drive Inter-operability test Projects, for Planning, Preparation and Test execution in Japan operators Lab and Field Test. 3. Analysis and report modem protocol related issues, to collaborate with team members in System Verification and modem R&D. 4. Track modem related issues and contribute the fast correction delivery. 5. Provide technical support, to lead prompt solution to internal/external customers

Power management IC design Audio IC design Data converter IC design high speed serdes IC design

- Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power. - Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. - Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. - DFT insertion, ATPG and gate-level simulation - Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). - Interact with Physical Design Engineers and provide them with timing/congestion feedback.

- RTL/Logic Integration and Verification - Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top level including SOC. - Use cdc tool to check RTL/SDC quality - Develop Power Intent Specification in UPF for the multi-vdd designs.

1. Define GPU compiler software architecture and interfaces. 2. Development/implement GPU compiler pipeline, linking and various optimizations/transformations. 3. Collaborate with Driver team, HW team to implement new API & HW features. 4. Collaborate with Driver team, HW team to improve/tune performance & power consumption. 5. Execute & deliver to meet milestones/schedules. 6. Analyze and debug code generation issues. 7. Analyze and influence future GPU architectures. 8. Construct reliable & trustable relationships across teams internally & externally. 9. The position can be located at Hsinchu or Taipei

1. 開發emulation/prototyping 相關的技術及使用流程 2. 建立CPU/GPU emulation/prototyping 驗證平台 3. 協助project team導入emulation/prototyping 技術 4. emulation/prototyping 使用及工具問題的支持 5. 管理 emulator 及prototyping 硬體與使用分配

1. 類比IC設計 2. 電源管理IC或ADC/PLL/Serdes類比電路整合及下線

1.顯示器/Branch 產品driver研發 2.Driver porting 與改善driver效能 3.負責Display Port driver開法跟問題排除 4.分析相容性問題

In this role, you will be a member of the System-on-Chip (SoC) platform modeling team, working with architecture, silicon and software engineering teams to shape the architecture of MediaTek‘s future SoCs. The position calls for independent performance modeling and analysis, documentation, and collaboration with teams across MediaTek. We are looking for highly motivated, hands-on individuals who are passionate about performance modeling of sophisticated SoC features in C++/Python to demonstrate their value and impact. Major Responsibilities: •Responsible for evaluating and improving the SoC performance and efficiency •Developing C++ performance models (C-model) of SoC architectural solutions and features. •Developing tests and microbenchmarks to represent the use cases to run on the model •Gathering and analyzing simulated performance data to evaluate architectural design alternatives under various SoC workloads and benchmarks. •Correlating performance of the SoC RTL infrastruct