清大專區

CPU Physical design, including 1. floorplan, P&R, CTS and timing closure 2. Physical verification

Optimize GPU performance, area/power for representative workloads (graphics and compute) from the perspectives of memory sub-system, low-power design/policy and implementation strategy. System modeling framework to simulate hardware with different accuracy/throughput tradeoffs at different stages of the design; supervise Performance/Power/Area investigation/validation and facilitate architecture/design decisions;

- Co-work w/ foundry/EDA vendors to define best PD imp recipes - Explore EDA tool new features and introduce to project team - Define proper FOM to project DTCO opportunities - Optimize PG structure for best resource and IR/EM concerns, including pillar types, via stacking layers - Help project team revise scripts, provide guidelines/checkers to check PD quality and feedback potential issues - Build physical-aware timing diagnosis utilities

In this role, you will be a member of the System-on-Chip (SoC) platform modeling team, working with architecture, silicon and software engineering teams to shape the architecture of MediaTek‘s future SoCs. The position calls for independent performance modeling and analysis, documentation, and collaboration with teams across MediaTek. We are looking for highly motivated, hands-on individuals who are passionate about performance modeling of sophisticated SoC features in C++/Python to demonstrate their value and impact. Major Responsibilities: •Responsible for evaluating and improving the SoC performance and efficiency •Developing C++ performance models (C-model) of SoC architectural solutions and features. •Developing tests and microbenchmarks to represent the use cases to run on the model •Gathering and analyzing simulated performance data to evaluate architectural design alternatives under various SoC workloads and benchmarks. •Correlating performance of the SoC RTL infrastruct

1. PMIC/SerDes 電路驗證 2. 類比電路驗證方法流程開發 3. Serdes/類比/RF電路之IR/EM 分析 4. 類比電路 Verilog-A 行為模型開發 5. 晶片-封裝 (WLCSP/CoWoS/3DIC/InFO 3D.)IR/EM 協同分析流程開發 6. 類比/射頻 CPM 模型化

In charge of technical program task execution to support team‘s goal

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

1. 先進製程技術製程開發 2. 先進封裝技術開發

1. SOC 整合工作, 從RTL到GDS 2. Synthesis / Timing closure / DFT / LEC / QC 3. 參與實體設計專案, floorplan/CTS/PnR 4. 使用Perl/Tcl 優化工作流程

多核心處理器系統驗證工程師: -Constrain random verification for 處理器和外圍設計電路 -以Coverage driven的低功耗驗證 -基於硬體電路架構的，Formal 靜態驗證

Responsible for digital design verification of power management IC 1. Define verification plan 2. Create testbench and verify design functionality 3. Develop verification environment 4. Explore DV methodology

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow

(1) Verification Planning 1.1 DSP platform module and/or system design 1.2 5G/6G modem module and/or system design (2) Testbench Build-Up 1.1 Constrained random verification by SystemVerilog/UVM usage 1.2 Reference modeling 1.3 Assertion check 1.4 Coverage closure (3) Coordination with Algorithm/Digital design/Software teams

1. 5G NR/Pre6G 通訊平台開發 (a) 5G gNodeB/UE 測試系統 開發 (b) L1 test mode演算法通訊平台開發 2. 5G NR通訊系統分析 (a) 5G NR實體層規格及流程驗證 (b) 基頻演算法設計驗證及訊號分析 (c) 整體系統效能驗證與流程分析 3. Modem 4/5G system level / physical layer issue analysis (a) Develop and integrate build and auto testing process (b) Collect / analyze system requirement & system design (c) Support urgent system function or performance problem

*Location: Taipei or Hsinchu 1. Build up methodology for early software development and system verification ahead of Hardware availability 2. Manage Hardware/Software interface to generate unified design spec. by collaborating with various domain experts and teams 3. Cross teams cooperation to define measurable factors of Hardware/Software change to optimize development efforts and project execution time 4. Create synergy from cross teams work to improve Hardware/Software quality and productivity 5. Cultivate innovation by driving cross-collaboration and execution of projects across multiple teams

1. 負責建立與改善軟體開發流程相關的資訊系統及自動化機制 2. 負責建置與維護〝持續整合(CI)〝、〝持續交付(CD)〝相關資訊系統與服務 3．新技術或軟體開發方法調研與導入，例如: AI, RPA等

1. Working on CPU implementation in advanced process nodes, physical designs and sign-off 2. Analyze and enhance design limits among speed, power and area 3. Collaborate with different designs, teams cross sites and countries.

1. 數位電路開發設計與整合 2. IP與系統層級驗證，包含FPGA和實際晶片 3. 數位流程執行與優化 4. IP文件與功能維護

Baseband手機系統應用與電源規格制定, 包含modem, PMIC and AP.

[職缺一] 1.IC 整合 2.IC設計整合流程改善 3. 數位IP設計/IC整合/系統驗證 [職缺二] 1.執行晶片sign-off流程 2.發展降低晶片功耗流程 3.整體晶片的靜態時序分析與收斂