清大專區

1. 整合IR 資訊和內部團隊合作解決 IR 問題 2. 產生並分析 power 資訊 3. 和客戶溝通 IR 相關的 methodology 並開發流程解決問題

1.PCB power related hardware design：Resonsible for design and develop hardware including circuit design, component evaluation and selection, customized component planning, layout review, etc. 2. System specification and design requirement collection. 3. System hardware verification and testing: function verification and power quality measurement. 4. Cross-organizational collaboration: Collaborate with IC design team, system team, SI/PI team, layout team, etc. to complete system design, production and verification. 5. Customer and related manufacturer support: including technical document writing, customer reference design support, on site support, etc.

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

1. 熟悉 2.5D 或是 3D 封裝技術, 開發和量產經驗 2. 從系統架構優劣比較, SIPI 或是測試或是 thermal 角度來提供適合的封裝技術

1. Serdes PMA IP architecture planning 2. Serdes PMA IP RTL coding 3. Serdes PMA IP front-end and back-end integration 4. Co-work with PCS and MAC design team and DV team for IP verification 5. Co-work with Analog design team for PHY co-simulation 6. Co-work with Algorithm team for algorithm implementation and bit-true verification

1. IEEE 802.3 Ethernet PHY & transceiver architecture & algorithm design 2. Digital signal processing of mixed-signal design 3. System simulation/model design for pre-silicon verification 4. System & algorithm design/simulation of high-speed I/F SerDes 5. Make contribution in standard organizations

1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams

1. Develop Die-to-die and UCIe digital IP for HPC SOC. 2. Integration of D2D controller and PHY to timing closure and DFT. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.

1. 優化數位 IC 設計 BE 流程與方法 2. 執行與管理數位 IC 設計 BE 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC，例如 CLP 3. 與 FE RTL designer 及 PD APR 團隊密切合作，針對 PPA（Performance, Power, Area）進行 design 及 clock structure 的優化 4. 將依應徵者的年資與專業經驗，提供不同的職級

1. SoC IC implementation 規劃設計 2. DFT 規劃設計 以及timing closure signoff 3. 設計方法流程開發及優化 4. 工作地點:新竹/台北

-規劃並執行高速介面（如 PCIe, USB, DP, UFS, CSI, UCIe）IP PHY 驗證。 -建立並維護測試平台，進行 System 與 Electrical 測試。 -使用 Scope, BERT, LA, Signal Analyzer 等儀器進行 Signal Integrity 與 Compliance Test。 -分析測試結果，協助 DE 及 SW 團隊解決問題。 -設計並開發硬體 PCB 評估板，支援系統驗證。

1. 與業務使用者進行需求訪談與流程討論 2. IT 相關服務的專案管理 3. 公司商務領域的數位化（應用系統、人工智慧、數據）轉型 1. Engagement and Process Discussion with Business Users. (FIN domain) 2. Project Management on IT Service 3. Digitalization (application, AI, data) Transformation for business domain

1. 5G modem 架與數位電路設計 2. CLK, 測試, Reset相關設計與規劃 3. 低功耗設計 4. 系統整合 RTL 到 Gate level, 含STA

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow

1.儀器設備的異常處理。 2.機台設備的日常維護及保養。 3.設備及其耗材的成本改善。 4.主管交辦事項。 5.需配合夜班：PM19:00~次日AM07:00。

1.既有客戶業務維運。(可長期派駐東南亞) 2.定期拜訪客戶，維繫穩定客戶關係。 3.開發潛在客戶，市場拓展，達成業績目標。 4.完整培訓，歡迎有熱誠及態度積極者，有意從事雲端與電子創新產業者。 5.可長期出差或派駐越南，需懂越南語。 1. Duy trì hoạt động kinh doanh của khách hàng hiện tại. (Có thể đồn trú lâu dài ở Đông Nam Á) 2. Thường xuyên ghé thăm khách hàng và duy trì mối quan hệ ổn định với khách hàng. 3. Phát triển khách hàng tiềm năng, mở rộng thị trường và đạt được mục tiêu hiệu suất. 4. Đào tạo đầy đủ, chào đón những người nhiệt tình, tích cực và có hứng thú làm việc trong ngành công nghiệp điện toán đám mây và đổi mới điện tử. Fivetech Technology Inc. specializes in fastener design and manufacturing for AI, electronics, and robotics, offering reliable Fivetech solutions for engineers worldwide.

1.當地日系客戶業務連絡/服務，東南亞日系客戶業務連絡/服務 2.當地業務擴展 3.須會日文(N2) 4.須有業務管理經驗2年以上

1.協助客戶投資規劃及建議 2.分析股票、債券、及其他金融投資市場之趨勢 3.提供多元且國際化的金融投資商品， 4.完整的理財資產配置分析，為客戶量身打造專業客製化的財富管理規劃。

1. 負責證券、期貨、選擇權之開發及接單。 2. 協銷各項金融商品（如：基金、保險及結構型商品）。 3. 協助客戶進行投資理財規劃。 4. 提供投資理財商品的諮詢服務。 5. 負責法人及VIP客戶的綜合資產管理。 (另依業績狀況核發業績獎金)

1.國內外ESG趨勢議題關注分析 2.參與編製永續報告書及揭露永續實績 3.參與或協助國內外永續相關獎項報獎 4.規劃統籌永續金融評鑑作業 5.永續相關專案及重要工作規劃與管理