清大專區

1. 進行射頻系統性能驗證工作，確保測試結果符合測試規範需求。 2. 與演算法及軟體部門合作開發與PA相關的省電技術。 3. 使用DPD技術改善PA的線性度與效率。 4. 支持重要客戶完成工廠校準時間的優化工作。 5. 撰寫高品質的技術文檔，並交給客戶支援單位以執行客戶支持。

1. AI SW task management and SW strategy development 2. Software developments of AI/GAI and its applications on automotive and Smart home products 3. OEM engagement for new application exploration 1. 負責AI SW任務管理與SW策略制定 2. 負責AI/GAI軟體開發及其在汽車、智慧家庭產品的應用 3. 參與OEM新應用探索

使用者體驗指標定義和品質保證，使用者體驗驗證工程師。 負責定義旗艦/高端/中端/低端的使用者體驗指標，預估未來用戶體驗發展，確保產品具競爭力。分析競品與客戶對接討論，開發測試手法與測試用例。 有Android phone 使用者體驗/功耗性能 設計或測試經驗，尤其有手機大廠相關測試規劃經驗者，將優先考慮。

1) 數據庫設計：參與數據庫的設計和架構規劃，以滿足業務需求。 故障排除：解決數據庫運行中的問題，並提供技術支持。 2) 數據庫維運：負責數據庫的日常維護工作，包括監控、備份、恢復和升級。 3) 性能監控：監控數據庫系統的性能，並進行必要的優化。 4) 合規性與安全：確保數據庫遵守相關法規和公司政策，並保護數據不受未授權訪問。

The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production.

In a flexible and supportive environment, one of your major responsibilities is to push the state of the art of learning theory. Furthermore, through collaboration with worldwide colleagues, you will have the rare opportunity to apply advanced Deep Learning theories to novel application areas such as AI-designed IC and General Intelligence Conversation. We welcome all ML/DL backgrounds, including computer vision, speech and NLP, and robotics.

In a flexible and supportive environment, one of your major responsibilities is to push the state of the art of learning theory, to obtain insights beyond mythical theories as well as to apply the right solution to novel application areas such as AI-designed IC and General Intelligence Conversation. Furthermore, you shall actively engage with worldwide colleagues and academics to nurture and build a collaborative and effective R&D environment. We welcome all ML/DL backgrounds, including computer vision, speech and NLP, and robotics.

• 負責高速SerDes的開發，包括韌體設計與演算法實現、IC功能驗證、系統效能優化以及客戶支援（熟悉架構、韌體、除錯、優化及測試相關工作） • 開發自動化驗證（使用C++、Python、C#和MATLAB） • 與類比/數位團隊合作，從原型設計到量產共同開發晶片 •協助客戶設計導入並支援量產

IC 測試開發工程師 負責高速數位、類比晶片測試程式開發(AP/compu AI/ASIC/…)，產品特性異常分析與改善 新產品導入量產與生產良率測試時間優化 俱獨立帶產品作業為佳。

1) 訂定通訊系統使用的CPU及系統架構 2) 開發RTOS、記憶體管理等系統相關服務 3) 開發CPU及平台模擬器 4) 分析軟體行為並增進系統效能 5) 開發CPU及系統相關的驅動及開機流程 6) 開發自動診斷系統問題的工具

1.負責 ASIC Memory IP Driver 軟體開發與 IC驗證環境 2.熟悉軟/韌體、優化、IC驗證 及 除錯 等工作項目 3.執行 IC bring up 與韌體系統整合的工作

We are looking for aspiring ML/DL candidates to join our team of researchers. The ideal candidate is open-minded, passionate about pushing learning theory, and keen on the opportunity to challenging convention. Your ideas shall be based on sound mathematical justification, yet can lead to scalable and practical solutions. In a flexible and supportive environment, one of your major responsibilities is to push the state of the art of learning theory. Furthermore, through collaboration with worldwide colleagues, you will have the rare opportunity to apply advanced Deep Learning theories to novel application areas such as AI-designed IC and General Intelligence Conversation. We welcome all ML/DL backgrounds, including computer vision, speech and NLP, and robotics.

1. CoWoS和2.5D封裝技術開發 2. 3D封裝技術開發 3. CPC/CPO封裝技術開發 4. 封裝技術整合和NTO管理

1. Package related structure stress analysis including warpage, material study. 2. Package and board level stress modeling for TCT, drop and vibration. 3. IC and package thermal analysis, modeling and characterization 4. Chip-Package-PCB thermal co-simulation and design. 5. System level thermal simulation 6. System level stress simulation

1. 屬於DE部門 2. 支援 WiFi/BT, 手機與 ARM computing等產品晶片開發計畫的FPGA與Emulation驗證工作與驗證技術開發 3. 主要為獨立貢獻者； 長期可依照潛力培養團隊領導能力，並有機會與全球科技產品的領導廠商有直接溝通合作的機會，可藉此培養個人與跨國的領導企業一起合作技術開發的能力。 4. 工作目標如下: a) 支援計畫功能與系統驗證與除錯 b) 規劃及協調驗證資源、項目及時程 c) 改善和加速multi-FPGA與Emulator工作流程 d) 增進FPGA與Emulator驗證效能 e) 研發SoC系統電路分析工具

. Familiar with ISO26262 safety software requirement breakdown for Cockpit and ADAS SoC, especially focus on SoC safety island . Customer Support: Provide technical support to customers and cross-departmental collaboration to ensure driver function development . Capable for the software architecture design and software safety analysis based on RTOS operating systems

負責PCIe軟體開發，硬體功能驗證，以及量產support. 1. FPGA/SoC 驗證 2. Linux/RTOS/Window PCIe driver 開發 3. 軟硬體問題分析與解決 4. 系統規格討論 5. 客戶問題支援

We are looking for AI hardware architect/designer to join our team and play a pivotal role in designing, developing, and optimizing architecture of the neural processing unit (NPU). As an architect/designer, you will be responsible for creating innovative hardware and software solutions that meet the performance, scalability, and efficiency requirements of our advanced NPU environment. The ideal candidate will have a strong background in computer architecture, microarchitecture, and digital design, as well as experience with industry-standard tools and methodologies. You are expected to transform novel ideas into practical proposals for future NPU products, and vet the proposals via prototyping. Extensive knowledge in compiler and operating system is a plus. International travel may be required.

【職務概述】 我們正在尋找具前瞻視野與創新精神的工程領導者，加入生成式 AI 應用平台團隊，打造企業級 GenAI 平台，協助內部團隊快速開發 AI 應用與智能代理，推動數位轉型。您將領導團隊建構關鍵能力，包括 RAG 框架、多代理分析平台與 HyperAutomation 模組，並推進多代理協作、模型路由、LLMOps 標準化與負責任 AI 治理。 【主要職責】 策略與領導：帶領跨領域團隊，制定技術藍圖與 KPI，導入 RAG 2.0、知識圖譜、AI Agent 協作等技術。 平台研發：設計與維運 RAG 框架、多模態分析 Agent、AI 自動化模組，導入 MCP、LangGraph 等前沿技術，強化平台效能與治理。 利害關係人協作：作為技術策略夥伴，協助事業單位導入 GenAI，與資料、業務、安全團隊共創 AI 解決方案，推動開發者生態與負責任 AI 架構。

1. CPU/GPU STA, high-speed & low-voltage timing signoff/ timing closure 方法流程設計 2. STA 流程開發及應用 3. high-speed/low-voltage timing signoff criteria開發及應用 4. 針對project的STA/timing signoff問題進行分析及改善