清大專區

1. 設計、開發和維護多媒體應用程式，包括但不限於Video playback, Image, playback。 2. 開發和優化 Android 平台上的多媒體應用程式，確保其性能和穩定性。 3. 開發和維護嵌入式系統上的多媒體應用程式，確保其在資源受限環境中的高效運行。 4. 與設計師、產品經理和其他工程師合作，確保多媒體應用程式的功能和使用者體驗達到高標準。 5. 進行多媒體技術的研究和創新，持續改進現有產品的性能和功能。 6. 撰寫和維護技術文件，確保程式碼的可讀性和可維護性。 7. 參與產品測試和除錯，確保產品的穩定性和可靠性。 8. 依據市場需求和用戶反饋，進行產品的優化和升級。

Wi-Fi架構和數位電路設計 整個晶片的時鐘、測試和重置規劃 低功耗數位設計 從RTL到閘級的SoC晶片整合，包括時序收斂和可測試性 設計方法和整合流程改進

We are looking for AI hardware architect/designer to join our team and play a pivotal role in designing, developing, and optimizing architecture of the neural processing unit (NPU). As an architect/designer, you will be responsible for creating innovative hardware and software solutions that meet the performance, scalability, and efficiency requirements of our advanced NPU environment. The ideal candidate will have a strong background in computer architecture, microarchitecture, and digital design, as well as experience with industry-standard tools and methodologies. You are expected to transform novel ideas into practical proposals for future NPU products, and vet the proposals via prototyping. Extensive knowledge in compiler and operating system is a plus. International travel may be required.

Do you want to be part of a smart and passionate team of researchers, advancing artificial intelligence to the next level of end-user experience in their daily lives? MediaTek Research Taiwan is seeking driven and brilliant young students to join our efforts by providing Internship placements. We are currently working on Natural Language Processing, AI for Chip Design and more! We hope you can join us as we embark on the a journey from research to product! The ideal candidate is open-minded, passionate about realizing AI in practical use cases, and looks forward to cutting-edge challenging problems. • You have experience on Frontend/Backend/Full-Stack Web programming • You have basic understanding of the foundations and engineering aspects of AI, hands on experience with machine Learning frameworks (PyTorch, Tensorflow, JAX) is a plus. • You are a proficient scientific communicator. You are committed to your goals and working in a team. • You are eager to tackle real-world applications with state of the art methodologies. We want your ideas to shine! As an Engineering Intern in our team, you will collaborate with our researchers and worldwide colleagues and develop applications and algorithms that make a real difference in everyday devices. Your developments would significantly enhance the experience of numerous end users across our product range.

Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products. • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. • Document on new flows and processes for AMS DV. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA

熟悉高速類比serdes 電路設計 例如 CTLE, CDR, DFE, PLL以及TX driver等

IC 測試開發工程師 負責高速數位、類比晶片測試程式開發(AP/compu AI/ASIC/…)，產品特性異常分析與改善 新產品導入量產與生產良率測試時間優化 俱獨立帶產品作業為佳。

聯發科技以先進多媒體技術聞名，數位視訊解碼更為多媒體技術中之重要一環，如果您對Multi-format Video decoder架構設計 / RTL implementation / 整合驗證有興趣，聯發科技誠摯邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

1. 負責NPU（神經網路處理器）軟體架構設計與開發，包含驅動程式、運算框架及相關工具。 2. 與硬體團隊合作，優化NPU軟硬體協同運作效能。 3. 針對AI模型推論流程，設計高效能的軟體解決方案。 4. 研究並導入最新的AI加速技術，提升NPU運算效能。 5. 撰寫技術文件，協助團隊理解架構設計與開發流程。 6. 支援跨平台（如Linux、Android等）NPU軟體移植與優化。 7. 參與問題分析與除錯，協助解決產品開發過程中的技術瓶頸。

數據分析及機器學習 (Big Data & Machine Learning)/流程機器人 (RPA) - Semantic Analysis/CPU / GPU 高效能運算叢集與平行運算技術優化/容器化(Container)技術實施與雲端(Cloud)應用系統推廣/資安漏洞檢測、惡意程式分析、駭客攻防技術研究/網路虛擬化及自動化程式開發

The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production.

1. Baseband algorithm development. 2. Ethernet PHY system architecture and algorithm design. 3. Communication system verification. 4. Architecture/algorithm design for low-power and high-speed communication system. 5. Digital signal processing of mixed-signal system.

(請留意：為加快面試安排時間，僅限定投遞5個職缺)我們在找這樣的你：對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣；勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

1. CPU system design and performance analysis 2. System bus architecture and integration 3. IP and system verification 4. Debug Architecture related IP design and integration

(請留意：為加快面試安排時間，僅限定投遞5個職缺)我們在找這樣的你：對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣；勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

1.負責 ASIC Memory IP Driver 軟體開發與 IC驗證環境 2.熟悉軟/韌體、優化、IC驗證 及 除錯 等工作項目 3.執行 IC bring up 與韌體系統整合的工作

1. IC功能驗證 2. 公板/建議線路設計開發(OrCAD/PADS) 3. 協助FAE/客戶解決硬體問題

1. 開發用於模擬手機/平板/車用SOC功率消耗的平台 2. 協助IP, SOC與軟體團隊，維護用於功耗分析的資料庫，開發相關工具以輔助跨團隊的資訊整合 3. 優化系統效能，輔佐系統功耗相關決策的進行

1、工作內容 • 規劃後端微服務架構 • 自動化流程部署設計 • 線上服務維護與除錯 2、團隊技術 • 使用 Gitea 進行版本控制及審核 • 使用 Jira 及 Confluence 控管專案進度及文件 • 使用 Gitea Action 打造自動化部署系統 • 使用 Go, Python, Node.JS 語言開發微服務架構 • 使用 Restful API, GraphQL 或 gRPC 進行服務溝通 • 資料庫使用 SQLite, Postgres 或 MySQL • 雲平台使用 Azure, AWS 或 GCP • 透過 Terraform, Pulumi 管理 Infrastructure • 使用 Grafana + Prometheus + Loki 監控各種服務狀態 • 使用 Kubernetes 部署服務 3、崗位要求： • 有 Go 語言或類似經驗，熟悉 gRPC 及 RESTful API • 有能力根據設計原則 design principles 及設計模式 design patterns 寫出 clean, maintainable, and performant code • 有建立大型且可擴展分布式系統，能理解熟悉微服務架構，Kubernetes，容器等相關技術 • 有使用 Kibana、Loki、Grafana、Tempo、OpenTelemetry 和 Prometheus 等可觀察性、監控、警報、追蹤和日誌記錄工具的經驗。 • 能夠指導團隊合作整體設計和程式碼架構，並不斷努力改進它，能夠為團隊編寫風格指南以供遵循。 • 五年以上相關軟體開發經驗，資工/電機相關科系畢業

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip