交大專區

We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

1. SOC platform 架構與RTL implementation 2. 負責 IP/子模組之 RTL 整合，組成 SoC (System-on-Chip) 或子系統的頂層設計。 3. 依據設計規格，串接不同來源或平台的 RTL，確保各模組間介面相容與功能正確。 4. 撰寫與維護整合 RTL 的頂層模組、配置腳本及連結測試環境。 5. 針對整合後的設計進行功能模擬、靜態時序分析（STA）、Lint、CDC 及等驗證工作，並協助 debug。 6. 與軟硬體、驗證、後端設計等團隊密切合作，確保整合流程順利與產品交付時程。 7. 編寫設計文件及協助設計交付相關事務。

Requirements Elicitation, Requirements Analysis, and Architectural Design - Analyze product requirements from customer - Discuss the expectations and requests with customer - Agree or reject the requirements - Make architectural design proposals

• Lead the DV effort of a high-end CPU project. • Manage, coach and guide DV engineers. Follow up status and keep up the schedule. • Architect and implement top-module testbenches and their components using UVM-based methods. • Lead the effort of building in-house BFMs to facilitate co-sim based module level verification. • Architect and implement formal verification based module level testbench. • Work with the design team to create testplans. Implement checkers/assertions/coverage check points. • Work with validation folks to improve design visibility

1. IC 整合 2. Package/Floorplan 整合

【職務內容】 1. 學習企業ERP系統作業流程，回覆處理使用者問題，提供專業解答與協助 2. 記錄並追蹤使用者問題和反饋，確保問題得到及時解決並進行後續跟進 3. 學習和提升個人專業知識，了解企業營運動態，提供給公司以供改進 【需求條件】 1. 具備 SQL資料查詢的基本能力，協助分析錯誤回報工程端 2. 分析與流程理解能力，具備企業營運與 ERP 流程的整合思維 3. 問題處理與故障排除能力，快速釐清問題本質與影響範圍 4. 擅長使用者需求訪談，釐清客戶痛點與使用落差 5. 具同理心與耐心、情緒穩定，能因應突發狀況解決問題 6. 可編寫使用手冊、SOP、Step by Step教學

1) 設計與建置 IT 客服 AI 支援方案 (如：服務品質監控、智慧助理)。 2) 應用 IaC (基礎設施即程式碼) 原則，管理終端設備及用戶問題排除。 3) 分析全球 IT 客服營運數據，優化服務流程及使用者體驗。 4) 持續研究與導入新技術趨勢並提出改善建議 (如：無密碼驗證、WoA、AI PC)。

1. High Speed digital design implementation 2. Integration from RTL to gate level, including flow QC, timing closure and issue analysis & solving 3. Signoff on design with mixed-signal interface 4. Design methodology and integration flow improvement

1. Develop Die-to-die and UCIe digital IP for HPC SOC. 2. Integration of D2D controller and PHY to timing closure and DFT. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.

1. Smartphone (Low Power Architect) and Automotive (Power control) 2. Not a management position 3. Short term:digital IP design/integration of power control IPs with zero bugs Long term:define power control arch for smartphone or automotive products develop new tech for power control

We are seeking skilled engineers for designing high-performance Virtualization and Interconnect Architecture and developing RTL for both Automotive and High-Performance Computing. Roles: 1. Develop, assess, and refine RTL to achieve performance, power, area, and timing goals. 2. Develop micro-architecture by exploring early high-level macro architectures, researching micro-architecture, and defining detailed specifications. 3. Coordinate co-design efforts between architecture, software, and hardware teams to achieve functional realization. 4. Develop and implement interconnect methodologies, such as simulation, emulation, implementation, and efficiency improvement.

1. Develop systematic methodology to alleviate design challenges, including FIP development, synthesis, DFT, physical implementation, sign-off, process what-if assessment, system performance evaluation, in advanced nodes or package. 2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies. 3. Explore new circuit architecture, EDA features and define improvement direction from MTK product requirements.

1. Package design and planning of various product. 2. Design & layout of BGA substrate. 3. Co-work with package houses for package design 4. Development of advanced package technology. 5. Package design platform development.

1. Model development (includes behavior modeling/ cycle approximate modeling/ power modeling) 2. ESL platform and simulation technology development. 3. Next-generation processor architecure prototyping and design exploration 4. Next-generation modem platform architecure prototyping and design exploration

NPU 編譯器工程師將負責MediaTek AI處理器的系統軟體和固件開發。 主要職責為開發以 MLIR 為基礎的 NPU compiler

Product 2.5D/3D/3.5D heterogeneous package development, LPDDR/HBM/IPM development for advanced package, product memory roadmap, package memory architecture , customized HBM development

We are looking for AI hardware architect/designer to join our team and play a pivotal role in designing, developing, and optimizing architecture of the neural processing unit (NPU). As an architect/designer, you will be responsible for creating innovative hardware and software solutions that meet the performance, scalability, and efficiency requirements of our advanced NPU environment. The ideal candidate will have a strong background in computer architecture, microarchitecture, and digital design, as well as experience with industry-standard tools and methodologies. You are expected to transform novel ideas into practical proposals for future NPU products, and vet the proposals via prototyping. Extensive knowledge in compiler and operating system is a plus. International travel may be required.

1. 領導IC專案的軟體開發（功能開發與驗證） 2. 追蹤開發進度並解決技術問題 3. 與軟體/韌體團隊合作 4. 有與IC驗證團隊合作經驗者尤佳

1. 開發 Android smartphone multimedia video system framework, driver and functions 2. 架構設計、分析並優化 Android smartphone multimedia video 效能 3. Video 功能驗證 4. 系統架構設計與問題分析

Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA