清大專區

1. Perform PMIC/SerDes circuit verification using advanced verification methodologies 2. Analog/Mixed-Signal circuit verification methodology / flow development. 3. Analog/Mixed-Signal circuit behavior model(Verilog-A/Verilog/SV) creation

人工處理器系統架構及RTL設計。 系統架構設計包含效能、功耗、D頻寬、以及面積分析。 並須負擔RTL實做。

In charge of technical program task execution to support team‘s goal

1. 新封裝供應商稽核及認證 2. 封裝供應商品質及可靠度管理 (品質異常事件處理, 變更管理, 例行性稽核, 評比等) 3. 新產品及技術導入品質及可靠度管理 4. 封裝供應商品質改善專案

我們想要找熱愛 AI 持續不斷學習新技術或打比賽, 聚焦長遠目標, 並且真正動手解決問題的人. 歡迎加入我們. We are looking for experienced Machine Learning/Deep Learning engineers. This is a technical role, and it requires a high willingness to learn state-of-the-art AI techniques and a skill to apply AI techniques to business applications/processes. This job opening encompasses a wide range of end-to-end ML pipeline activities, including framing AI problems, data collection/preprocess/exploration, model development/evaluation, model deployment/monitor.

•我們在一個節奏快且敏捷的工作環境, 聚焦長期目標, 動手解決真正問題, 將 AI 落地在真實世界, 並發表論文在頂級會議與期刊. 歡迎加入我們. •此職位將協助部門AI專案之推廣相關事宜, 包含但不限於服務部屬與測試, 模型狀況監測. •This is a technical role, and it requires a high willingness to learn state-of-the-art AI techniques and a skill to apply AI techniques to business applications/processes. This job opening encompasses a wide range of end-to-end ML pipeline activities, including framing AI problems, data collection/preprocess/exploration, model development/evaluation, model deployment/monitor. Our major responsibilities include (1) landing AI in real world (2) publication at top conference/journal (DAC, IEEE/TCAD, ICLR, ICML…). Here, you will be working in a fast-paced and agile environment which needs a mindset of a startup. Together with worldwide colleagues you will deliver everything from state-of-the-art algorithms to quicker value proving solutions. •This position will assist in the promotion of the departments‘s AI project, including but not limited to service deployment, and model status monitoring.

1. 5G NR/Pre6G 通訊平台開發 (a) 5G gNodeB/UE 測試系統 開發 (b) L1 test mode演算法通訊平台開發 2. 5G NR通訊系統分析 (a) 5G NR實體層規格及流程驗證 (b) 基頻演算法設計驗證及訊號分析 (c) 整體系統效能驗證與流程分析 3. Modem 4/5G system level / physical layer issue analysis (a) Develop and integrate build and auto testing process (b) Collect / analyze system requirement & system design (c) Support urgent system function or performance problem

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow

(1) Verification Planning 1.1 DSP platform module and/or system design 1.2 5G/6G modem module and/or system design (2) Testbench Build-Up 1.1 Constrained random verification by SystemVerilog/UVM usage 1.2 Reference modeling 1.3 Assertion check 1.4 Coverage closure (3) Coordination with Algorithm/Digital design/Software teams

1. 先進製程技術製程開發 2. 先進封裝技術開發

1. SOC 整合工作, 從RTL到GDS 2. Synthesis / Timing closure / DFT / LEC / QC 3. 參與實體設計專案, floorplan/CTS/PnR 4. 使用Perl/Tcl 優化工作流程

1. 先進製程(＜N5)的可測試電路實作流程開發 2. 先進製程(N4/N3)可測試錯誤模型的研究與實作 3. 針對超高速與超低壓電路錯誤模型的研究與實作 4. 量產測試dppm分析與除錯, 測試效率的改善 5. 系統軟硬體測試的分析與除錯

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

多核心處理器系統驗證工程師: -Constrain random verification for 處理器和外圍設計電路 -以Coverage driven的低功耗驗證 -基於硬體電路架構的，Formal 靜態驗證

Responsible for digital design verification of power management IC 1. Define verification plan 2. Create testbench and verify design functionality 3. Develop verification environment 4. Explore DV methodology

*Location: Taipei or Hsinchu 1. Build up methodology for early software development and system verification ahead of Hardware availability 2. Manage Hardware/Software interface to generate unified design spec. by collaborating with various domain experts and teams 3. Cross teams cooperation to define measurable factors of Hardware/Software change to optimize development efforts and project execution time 4. Create synergy from cross teams work to improve Hardware/Software quality and productivity 5. Cultivate innovation by driving cross-collaboration and execution of projects across multiple teams

1. 無線網通系統, 數位設計 2. Micro Processor, 系統架構, low power/效能分析 3. SOC 整合/驗證 1. Wireless connecitivity system (GPS or BT or WiFi or FM or NFC or 60G) baseband or MAC design 2. uP/DSP system/peripheral architecture and digital circuit design 3. SoC chip integration / Verification

(1) 負責WLAN網路架構系統評估 (2) 負責Wi-Fi7 新功能開發與軟硬體架構規劃 (3) 負責新規格 Wi-Fi7 無線網路系統軟硬體雛型系統開發, 模擬與系統效能分析

RF system application, including 4G/5G RF系統應用

1. 撰寫或移植裝置驅動程式 2. 撰寫硬體模組測試程式 3. 進行硬體模組測試及驗証 4. 分析系統問題 5. 分析及改善系統功粍或效能 6. 平台安全架構 (SMMU, Hypervisor, TEE)