交大專區

About the Role: Bring your GPU driver expertise and work closely with our Architecture and Micro-architecture teams. In this role, you will contribute across the GPU software stack and help extract maximum performance from the silicon while supporting the development of our next-generation GPU designs. This is not a siloed driver role. You will have opportunities to work across industry-standard graphics and compute APIs, kernel-mode drivers, GPU firmware, performance optimization, and hardware/software integration. What You‘ll Do — The Full Stack: • API Layer: Develop, debug, and optimize features for industry-standard APIs including Vulkan, DirectX, OpenGL ES, and OpenCL. • Kernel & Firmware: Work on kernel-mode drivers and GPU firmware to improve hardware control, stability, scheduling, memory management, and execution efficiency. • Performance: Analyze and optimize bottlenecks across the stack, including driver overhead, memory bandwidth, GPU scheduling, compute throughput, and power/performance tradeoffs. • Cross-Team Collaboration: Work closely with Architecture, Micro-architecture, Compiler, and GPU Model teams to validate GPU behavior, debug complex issues, and improve software/hardware interaction. • System-Level Debugging: Investigate issues across user-mode drivers, kernel-mode drivers, firmware, and hardware models to improve stability, correctness, and performance. Why This Role? • No Silos: You are not restricted to only one layer of the stack. You will have the opportunity to work across APIs, drivers, firmware, and performance. • Hardware-Software Impact: Your work will help the software stack fully utilize GPU hardware capabilities. • Next-Gen GPU Exposure: You will collaborate with architecture, compiler, and modeling teams on technologies that shape future GPU products. Ready to work across the entire GPU stack? Apply today.

Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting

1. CPU system design and performance analysis 2. AMBA System bus architecture and integration 3. IP and system design and verification

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis 2. Basic knowledge of analog design 3. Mixed signal design experience is a plus. 4. SoC architecture exploration and performance analysis experience is plus. 5. Post-silicon mass production experience ((Ex: DFT, CP, FT)) is a plus. 1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 2 . 具類比IC設計的基本知識 3. 混和訊號IC設計經驗是加分項 4 . 系統架構分析經驗是加分項 5 . 具IC量產相關經驗(Ex: DFT, CP, FT)是加分項

職責要求 1. 資料科學團隊管理 - 建立模型開發流程，涵蓋需求確認、資料探索、模型設計、驗證、部署、監控與迭代。 - 管理專案進度、資源分配、風險控管與跨部門協作。 2. AI / Data Product Roadmap 規劃 - 推動 Predictive AI、Interpretive AI、Generative AI 與 Agentic AI 在媒體場景中的應用。 - 建立模型效能、資料品質、使用者採用與商業成效的追蹤機制。 3. 精準廣告與預測式 AI - 帶領團隊發展受眾分群、使用者興趣預測、廣告反應預測、高價值受眾辨識與 campaign performance analysis。 - 與廣告業務、廣告產品、ad operations 及資料工程團隊合作，將模型能力轉化為可銷售、可交付、可追蹤的廣告產品與客戶洞察。 4. 內容推薦與個人化 - 發展使用者閱讀行為分析、內容特徵建模、個人化推薦、熱門內容推薦、冷啟動策略與相似內容推薦。 - 支援首頁、文章頁、App、電子報與推播等場景的推薦邏輯與 A/B 測試。 - 確保推薦模型兼顧點擊成效、內容品質、使用者體驗、內容多樣性與編輯價值。 5. 新聞室生成式 AI 應用 - 帶領團隊發展文章分類、內容標籤、摘要生成、標題建議、議題聚合、受眾匹配與新聞室決策輔助功能。 - 建立生成式 AI 輸出品質評估、編輯回饋機制、人工覆核流程與風險控管。 - 確保 AI 作為輔助工具支援新聞專業，而非取代編輯判斷。 6. 模型治理與負責任 AI - 建立模型文件化、資料來源說明、模型限制、適用範圍與版本管理機制。 - 推動資料品質檢查、模型漂移監測、GenAI 輸出品質評估、偏誤風險管理與異常 fallback 機制。 7. 跨部門協作 - 與新聞室共同定義 AI 輔助工具的應用場景、成功指標與回饋機制。 - 與廣告業務合作，將資料洞察與受眾模型轉化為銷售工具、提案素材與廣告商品。 - 與平台、產品與工程團隊合作，推動推薦實驗、產品優化、模型整合與成效追蹤。 任職資格 1. 具備資料科學、AI、機器學習或資料產品團隊管理經驗。 2. 能帶領團隊從問題定義、模型開發、驗證、部署到成效追蹤。 3. 具備跨部門專案管理與 stakeholder management 能力。 4. 熟悉資料科學、機器學習、推薦系統、NLP 或生成式 AI 應用。 5. 熟悉 Python、SQL 與資料處理流程。 6. 熟悉 scikit-learn、XGBoost、LightGBM、TensorFlow、PyTorch 或類似工具。 7. 熟悉 Google Cloud Platform，並了解 AWS 或其他 cloud data platform。 8. 具備模型部署、MLOps、pipeline、API、batch inference、monitoring 或 production AI 經驗。 9. 能審查模型設計、評估方法、技術文件與實驗結果

We are seeking skilled engineers for designing high-performance Virtualization and Interconnect Architecture and developing RTL for both Automotive and High-Performance Computing. Roles: 1. Develop, assess, and refine RTL to achieve performance, power, area, and timing goals. 2. Develop micro-architecture by exploring early high-level macro architectures, researching micro-architecture, and defining detailed specifications. 3. Coordinate co-design efforts between architecture, software, and hardware teams to achieve functional realization. 4. Develop and implement interconnect methodologies, such as simulation, emulation, implementation, and efficiency improvement.

1. 數位晶片設計流程與整合 2. 熟悉低功耗的設計流程(和架構)

1. 規劃量產測試以及量產functin pattern porting 2. 測試以及驗證IC功能，性能，以及功耗等等相關測試 3. 分析測試資料以及釐清相關測試的問題，並分析良率問題以及良率改善建議 4. AVS low power的設計

1. 高速信號介面及系統電源應用規劃整合、除錯等手機系統應用. 2. Baseband系統驗證方法開發、電源規格訂定及驗證規劃 3. 客戶參考設計文件訂定及量產相關技術支援.

1. 具備先進製程SoC 晶片 top flow 的專業知識。 2. Advance CTS design 3. 開發先進制程的 Power Mesh 經驗。

1. Work on 7nm~3nm physical design implementation, methodology, and sign-off 2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. IC 整合 2. Package/Floorplan 整合

1. 智慧型手機系統記憶體與儲存: DRAM (LPDDR4, LPDDR5, LPDDR6...) / Storage (UFS, eMMC...)驗証 2. 系統驗証方法研究與開發 3. 規畫驗証計畫 (test plan, test case) 4. 自動化測試環境開發

1. Package design and planning of various product. 2. Design & layout of BGA substrate. 3. Co-work with package houses for package design 4. Development of advanced package technology. 5. Package design platform development.

In a flexible and supportive environment, one of your major responsibilities is to push the state of the art of learning theory. Furthermore, through collaboration with worldwide colleagues, you will have the rare opportunity to apply advanced Deep Learning theories to novel application areas such as AI-designed IC and General Intelligence Conversation. We welcome all ML/DL backgrounds, including computer vision, speech and NLP, and robotics.

1. 應用正規方法在硬體或軟體的驗證上 2. 正規方法文獻回顧與論文分析以改善目前的使用限制 3. 規劃安排跨部門的技術教學與討論課程 4. 相關的文件撰寫與審查修改 5. 此職缺之薪資起始水準為NT$29500~50000，但仍會視人選之學經歷背景調整核定。

1.負責 ASIC Memory IP Driver 軟體開發與 IC驗證環境 2.熟悉軟/韌體、優化、IC驗證 及 除錯 等工作項目 3.執行 IC bring up 與韌體系統整合的工作

We are looking for AI hardware architect/designer to join our team and play a pivotal role in designing, developing, and optimizing architecture of the neural processing unit (NPU). As an architect/designer, you will be responsible for creating innovative hardware and software solutions that meet the performance, scalability, and efficiency requirements of our advanced NPU environment. The ideal candidate will have a strong background in computer architecture, microarchitecture, and digital design, as well as experience with industry-standard tools and methodologies. You are expected to transform novel ideas into practical proposals for future NPU products, and vet the proposals via prototyping. Extensive knowledge in compiler and operating system is a plus. International travel may be required.

1. 數位電路設計 2. 多媒體電路設計 3. 系統整合

Fully accountable with the team to deliver highly competitive ARM based CPU IP. Implementation skill required ranged from RTL, synthesis, DFT, Floorplan, Placement, CTS, Routing, Timing Closure, and physical verification.