交大專區

1.熟悉飯店各項工程(機電、弱電監控、給污排水、空調照明、消防設備)等相關系統操作及專案規劃建議。 2.督導工程部值班人員工作分配、排班與專業培訓，建立專業團隊。 3.管理設施預防性維護計畫，推動節能及資源優化。 4.檢查與執行各項安全、消防法規，配合相關合格檢查，主動追蹤設施風險與改善措施。 5.配合公司政策，確實執行各項工程進度追蹤與督導並回報提供上級參考。 6.協助公司與工程相關之政府單位關係建立與完成飯店年度各項設備定期檢查及保養維修。 7.統籌預防性保養計畫、能源管理、預算編列及裝修工程，具備機電專業能力。 8.協調各部門等跨部門需求，及時回應並排除現場故障，支援特殊營運需求及活動。 9.定期完成設備檢查、維修紀錄、能耗分析與部門營運報表並回報。

職責要求 1.行銷活動規劃整合，團隊工作分配並掌握活動執行進度，並擬定具體執行方案。 2.品牌電商/會員行銷/大型電子商務平台，合作通路建置開發與營運管理。跨境電商經營 。 3.網路行銷策略擬定、執行與成效分析調整。 4.行銷活動排程，規劃商品活動設計與發想。 5.負責行銷企劃案的規劃，籌備與執行公司內外的行銷活動與通路活動。 6.具備相關合作洽談溝通能力。 7.網路通路市場經營，電商網購網站拓展。 任職資格 1.擅長工具：PHP、MySQL、Dreamweaver、JavaScript、CSS、Adobe Photoshop、Illustrator

1.自動化設備機構設計開發，具獨立設計開發能力。 2.機台驗證測試與修改。 3.圖面繪製及相關技術文件產出。 4.配合團隊產品優化與技術支援。

職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

1.執行新開發案/新產品設計 2.設計變更機構/零件 3.整理部門資料、圖面、BOM表 4.主管交辦事項

1. 建立電控物料表 2. 電路圖規劃 3. PLC程式編輯與修改 4. 編製工程文件、技術文件、故障排除手冊 5. 配合應用工程人機介面開發 6. 檢驗標準制定 7. 出機備檔 8. 維修服務

1. 加工流程圖規劃，程式編輯 2. 基本電路圖查修，故障排除 3. 各規格控制器操作(新代、西門子、Fanuc等) 4. 售服調機 5. 配合電控人機介面開發 6. 依照主管指示安排作業。

1.具客戶行為分析與應用相關經驗 2.具商業議題敏銳度者佳 3.具備統計知識(假設檢定、機率、抽樣) 4.熟悉資料探勘方法並具備結構化資料庫概念 5.具備邏輯及問題分析能力尤佳 6.具SQL程式語言能力 7.具R、Python等程式語言者佳

【工作內容】 1. 統籌集團資訊系統、主機、網路、資料庫及各營運點資訊設備之維運管理，確保資訊環境穩定、安全、可靠。 2. 負責 SAP、PowerBI、BPM / Flow 及相關企業管理系統之開發、維護、應用與優化，協助各部門提升資料應用、管理報表及流程數位化能力。 3. 規劃並執行資訊安全管理，包括帳號權限、資料備份、網路安全、系統存取控管、資安風險評估及異常事件處理。 4. 依集團營運需求，評估並推動資訊系統導入、系統整合、流程改善及數位化專案，提升營運效率與使用者體驗。 5. 建立並維護資訊管理制度及標準化作業流程，提升資訊治理品質與跨部門協作效率。 6. 負責資訊預算規劃、成本控管、專案進度追蹤、外部廠商管理及服務品質監督。 7. 與客房、餐飲、財務、採購、人力資源、行銷公關、工物內裝及各營運單位合作，理解營運需求並提供資訊解決方案。 8. 負責創新科技部團隊管理、人員分工、工作進度追蹤、人才培育及績效管理。 【我們期待的人選】 我們期待此職位不只是傳統 IT 維運主管，而是能協助集團建立穩定、安全、有效率的資訊治理架構，並推動數位化、資料化與流程優化的總部型科技管理主管。

職責要求 1、具備與使用單位溝通與整合能力 2、具備MES導入經驗 3、負責MES報表開發 4、負責MES系統日常作業與問題處理 任職資格 1、熟悉使用Oracle DB資料庫 2、熟悉C＃(.Net Core/.Net Framework) 3、熟悉Web API後臺開發設計 4、具REACT前臺開發設計經驗 5、具備PLC/MODBUS/OPCUAT通訊觀念或相關設備整合經驗尤佳 6、具備工廠端系統概念及機連網經驗者佳 7、領導與溝通協調，具管理能力

1.Designs IC sockets and components using design tool provided. 2.Conduct performance forecast, simulation, and analysis 3.Modifies drawings based on NBOs. 4.Measures locally made parts and customer packages. 5.Measures IC socket and components. 6.Translates engineering documents into English (by special assignment). 7.Verifies customer package drawing to existing socket drawing. 8.Modifies and assembles parts for IC sockets. 9.Act as global engineering members. 10.Provides technical support for Sales, field support as needed. 11.Provides technical support to customers through phone, email, and on-site Work. 12.Interacts with vendors on issues of piece parts manufacturing. 13.Provides quality check for assembly and piece parts. 14.Test new products. 15.Improve design quality and speed.

職責要求 1. 外包需求規格與範疇定義：將公司的產品想法，轉譯為清晰的「功能需求規格書（PRD）」與「驗收標準」，避免外包廠商認知落差。 2. 外包時程與進度控管：制定專案、追蹤外包團隊的開發進度（網頁端、Unity端、美術端），控管專案預算與交付時間。 3. 跨技術平台溝通協調：作為公司與外包團隊的技術橋梁，督促廠商處理「網頁前端(React/Vue) ⇄ Unity 3D 引擎」與「雲端資料庫(JSON數據) ⇄ 3D 畫布」的串接。 4. 系統品質驗收與測試 (QA/QC)：依據合約階段進行功能驗收。特別針對 3D 模型在網頁上的載入速度（WebGL 優化）、家具拖拉流暢度及帳號登入安全性進行把關。 5. 系統點交管理：負責外包結案時的源碼（Source Code）、3D素材（FBX/材質）及部署權限的點交與公司內部歸檔。 任職資格 必備技能與條件： 1. 專案管理與外包管理經驗 (核心)，具備 4 年以上軟體或網頁產品經理 (PM) / 專案經理經驗。 2. 技術與 3D 知識背景(關鍵辨識度)，懂 Unity 3D 引擎的基本運作邏輯與 WebGL 網頁發布概念（不需手寫 C# 程式，但要聽得懂廠商的技術回報） 3. 懂 Web 網頁開發基本架構：了解前後端分離、API 觀念，以及資料如何透過 JSON 結構在網頁與 3D 引擎間傳遞 • 核心工具： - JavaScript、Python、MySQL、懂 Unity 3D 引擎的基本運作邏輯與 WebGL 網頁發布概念，懂 Web 網頁開發基本架構 -了解前後端分離、API 觀念，以及資料如何透過 JSON 結構在網頁與 3D 引擎間傳遞。 • 加分條件：具備生成式 AI（Generative AI）相關應用經驗或熟悉者尤佳。

- Optimize GPU performance, area/power for representative workloads (graphics and compute) from the perspectives of memory sub-system, low-power design/policy and implementation strategy. - System modeling framework to simulate hardware with different accuracy/throughput tradeoffs at different stages of the design; supervise Performance/Power/Area investigation/validation and facilitate architecture/design decisions

Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.

Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

1. Make test pattern plan to cover system bring-up for MP (CP/FT, system test, DVT, HQA, correlation, DPPM reduction) 2. Debug post-silicon issue to identify design weakness and solution finding 3. Correct post-silcion measurement vs. pre-silicon simulaiton, including process, performance, power.

1. 負責CP/FT/SLT/Burn-in/Socket 測試配件開發與驗證 2. 先進封裝測試配件新技術新需求開並導入量產 3. 測試配件供應商管理