交大專區

職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

1.執行新開發案/新產品設計 2.設計變更機構/零件 3.整理部門資料、圖面、BOM表 4.主管交辦事項

1. 建立電控物料表 2. 電路圖規劃 3. PLC程式編輯與修改 4. 編製工程文件、技術文件、故障排除手冊 5. 配合應用工程人機介面開發 6. 檢驗標準制定 7. 出機備檔 8. 維修服務

1. 加工流程圖規劃，程式編輯 2. 基本電路圖查修，故障排除 3. 各規格控制器操作(新代、西門子、Fanuc等) 4. 售服調機 5. 配合電控人機介面開發 6. 依照主管指示安排作業。

1.具客戶行為分析與應用相關經驗 2.具商業議題敏銳度者佳 3.具備統計知識(假設檢定、機率、抽樣) 4.熟悉資料探勘方法並具備結構化資料庫概念 5.具備邏輯及問題分析能力尤佳 6.具SQL程式語言能力 7.具R、Python等程式語言者佳

【工作內容】 1. 統籌集團資訊系統、主機、網路、資料庫及各營運點資訊設備之維運管理，確保資訊環境穩定、安全、可靠。 2. 負責 SAP、PowerBI、BPM / Flow 及相關企業管理系統之開發、維護、應用與優化，協助各部門提升資料應用、管理報表及流程數位化能力。 3. 規劃並執行資訊安全管理，包括帳號權限、資料備份、網路安全、系統存取控管、資安風險評估及異常事件處理。 4. 依集團營運需求，評估並推動資訊系統導入、系統整合、流程改善及數位化專案，提升營運效率與使用者體驗。 5. 建立並維護資訊管理制度及標準化作業流程，提升資訊治理品質與跨部門協作效率。 6. 負責資訊預算規劃、成本控管、專案進度追蹤、外部廠商管理及服務品質監督。 7. 與客房、餐飲、財務、採購、人力資源、行銷公關、工物內裝及各營運單位合作，理解營運需求並提供資訊解決方案。 8. 負責創新科技部團隊管理、人員分工、工作進度追蹤、人才培育及績效管理。 【我們期待的人選】 我們期待此職位不只是傳統 IT 維運主管，而是能協助集團建立穩定、安全、有效率的資訊治理架構，並推動數位化、資料化與流程優化的總部型科技管理主管。

職責要求 1、具備與使用單位溝通與整合能力 2、具備MES導入經驗 3、負責MES報表開發 4、負責MES系統日常作業與問題處理 任職資格 1、熟悉使用Oracle DB資料庫 2、熟悉C＃(.Net Core/.Net Framework) 3、熟悉Web API後臺開發設計 4、具REACT前臺開發設計經驗 5、具備PLC/MODBUS/OPCUAT通訊觀念或相關設備整合經驗尤佳 6、具備工廠端系統概念及機連網經驗者佳 7、領導與溝通協調，具管理能力

1.Designs IC sockets and components using design tool provided. 2.Conduct performance forecast, simulation, and analysis 3.Modifies drawings based on NBOs. 4.Measures locally made parts and customer packages. 5.Measures IC socket and components. 6.Translates engineering documents into English (by special assignment). 7.Verifies customer package drawing to existing socket drawing. 8.Modifies and assembles parts for IC sockets. 9.Act as global engineering members. 10.Provides technical support for Sales, field support as needed. 11.Provides technical support to customers through phone, email, and on-site Work. 12.Interacts with vendors on issues of piece parts manufacturing. 13.Provides quality check for assembly and piece parts. 14.Test new products. 15.Improve design quality and speed.

職責要求 1. 外包需求規格與範疇定義：將公司的產品想法，轉譯為清晰的「功能需求規格書（PRD）」與「驗收標準」，避免外包廠商認知落差。 2. 外包時程與進度控管：制定專案、追蹤外包團隊的開發進度（網頁端、Unity端、美術端），控管專案預算與交付時間。 3. 跨技術平台溝通協調：作為公司與外包團隊的技術橋梁，督促廠商處理「網頁前端(React/Vue) ⇄ Unity 3D 引擎」與「雲端資料庫(JSON數據) ⇄ 3D 畫布」的串接。 4. 系統品質驗收與測試 (QA/QC)：依據合約階段進行功能驗收。特別針對 3D 模型在網頁上的載入速度（WebGL 優化）、家具拖拉流暢度及帳號登入安全性進行把關。 5. 系統點交管理：負責外包結案時的源碼（Source Code）、3D素材（FBX/材質）及部署權限的點交與公司內部歸檔。 任職資格 必備技能與條件： 1. 專案管理與外包管理經驗 (核心)，具備 4 年以上軟體或網頁產品經理 (PM) / 專案經理經驗。 2. 技術與 3D 知識背景(關鍵辨識度)，懂 Unity 3D 引擎的基本運作邏輯與 WebGL 網頁發布概念（不需手寫 C# 程式，但要聽得懂廠商的技術回報） 3. 懂 Web 網頁開發基本架構：了解前後端分離、API 觀念，以及資料如何透過 JSON 結構在網頁與 3D 引擎間傳遞 • 核心工具： - JavaScript、Python、MySQL、懂 Unity 3D 引擎的基本運作邏輯與 WebGL 網頁發布概念，懂 Web 網頁開發基本架構 -了解前後端分離、API 觀念，以及資料如何透過 JSON 結構在網頁與 3D 引擎間傳遞。 • 加分條件：具備生成式 AI（Generative AI）相關應用經驗或熟悉者尤佳。

• 主導 6G 頻譜接取（spectrum access）、初始接取（initial access）、能源效率（energy efficiency）或 MIMO 等技術的開發與 3GPP 標準化，推動功能從概念落實至正式核定的規格。 • 在 3GPP 及其他標準組織中撰寫並推動技術提案（contributions），並凝聚共識以促成其採納。 • 爭取並擔任 3GPP 關鍵領導職位——包含 feature lead 與 rapporteur——並代表公司策略性競選。 • 跨 3GPP 各工作組（working groups），以及在標準化團隊與產品實現團隊之間進行協作，確保技術可行性與設計一致性。 • 指導資淺工程師熟悉標準化流程與技術開發。

Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.

在系統級封裝（SiP）與 PCB 佈局的極早期階段，就將 EMC 對策融入設計中。您將與 IC 設計、封裝、軟韌體及功能安全（ISO 26262）團隊緊密合作，確保我們的產品能一次性通過全球最嚴苛的 Tier-1 與車廠認證標準。 關鍵工作內容 (Key Responsibilities) 1. 系統設計 (Board Co-Design for EMC)： • 設計與優化電源分配網路（PDN），制定去耦電容（Decoupling Capacitor）的佈局與選型策略，從源頭降低電磁輻射（EMI）與提升耐受性（EMS）。 2. 先進電磁模擬與預測 (Advanced EM Simulation)： • 在投片（Tape-out）與洗板（PCB fabrication）前，利用 3D 電磁模擬軟體（如 Ansys, CST）進行系統級的輻射與傳導雜訊模擬分析，提前發現並消除潛在的 EMC 風險。 3. 車規標準合規與驗證 (Automotive Standard Compliance)： • 確保產品符合全球車規 EMC 標準，包含 CISPR 25, ISO 11452, ISO 7637, ISO 16750 以及各大車廠（OEM）的客製化規範。 • 將系統級（System-level）的車規要求，向下拆解並定義為 IC 與 SiP 模組級（Component-level）的設計規格。 4. 實驗室除錯與跨部門技術指導 (Debugging & Cross-functional Leadership)： • 帶領團隊在無響室/電波暗室進行產品測試。當面臨 EMI/EMS 挑戰時，能迅速進行根因分析（Root Cause Analysis）。 • 提出軟硬體整合的解決方案（例如指導韌體團隊設定 Spread Spectrum Clocking, SSC 展頻技術，或調整硬體濾波器），並驗證其有效性。

- 負責資料中心相關 IP 整合，涵蓋從合成、DFT 至 GDS 交付完整流程 - 負責先進製程晶片整合，涵蓋從synthesis QC Sign-off & Tapeout

1. 管理 IT 團隊日常運作，建立並落實標準化流程 2. 規劃與優化資訊系統架構、系統整合與資安防護 3. 主導或參與 ERP 等大型資訊專案 4. 執行 IT 專案管理 5. 跨部門溝通協調，整合需求並提供系統解決方案 本職務為公司關鍵支援角色，能實際參與核心系統與流程優化，對企業營運具實質影響。

車用電源系統，車用電子，12V or 48 V 等產品的系統電源設計/驗證之電源應用工程師，需與Designer 、PM、SW 等單位討論系統的電源設計的競爭力的分析，並驗證系統Power solution，撰寫design note 等文件，協助處理客戶開案並量產的相關系統電源問題。

車用IC 於座艙系統的硬體PCB module應用開發事項，針對SOC system on module board 的PCB 開發。負責PCB Module 的電路設計，Layout 相關的review, 並基於Module 的DFM rule產出相關的設計文件。

1. Direct manager and project lead 2. Cloud data center product 3. DFT task force 4. short term: top DFT flow implement and signoff long term: DFT/test mode planning and new tech development.