交大專區

無線網通晶片設計/整合/驗證

1. Smart phone系統low speed (SPI/SPMI/I2C/I3C/…)和SerDes (CSI)驗証 2. 系統驗証方法研究與開發 3. 規畫驗証計畫 (test plan, test case) 4. 自動化測試環境開發

1. Serdes IP設計開發, IC功能驗證與系統效能改善, e.g. 50G/100G/200G/300G/400G. 2. 與類比/數位/演算法團隊合作共同開發晶片從雛型設計到量產 3. 負責實作演算法或韌體設計,並在設計階段協助開發團隊建立模擬模型來增加驗證涵蓋率 4. 設計自動化驗證高速介面並除錯, 並支持IP導入產品與客戶應用

1. Architecture design and RTL implementation for Smartphone and automotive chip 2. Smartphone SoC and mobile computing platform design. 3. System bus and high speed interface designs

1. 開發設計 Security HW IP 2. 協助 HW IP 驗證 3. 執行 IC 設計整合流程

1. 面板傳輸規格介面技術開發 2. TCON傳輸規格介面技術開發

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

AI Model development, system level modeling and HW/SW system level bottleneck analysis

我們的使命是運用機器學習與生成式 AI (GenAI) 技術，協助 MediaTek 提升研發效率與工程品質。你將與各部門緊密協作，將業務痛點轉化為 AI 專案，並設計從 PoC 到正式上線的高可用性解決方案，實現可量化的生產力提升。 Key Responsibilities : • 針對研發與營運場景協助 AI 系統架構設計與評估，整合 LLM、Agent 與多模態 AI 等前沿技術，制定最佳落地策略。 • 運用紮實的軟體開發能力負責 GenAI 應用開發與落地，透過 LLM API 敏捷整合至現有工作流與產品中。 • 導入 AI 開發輔助工具並建置 LLMOps 基礎設施，建立 ML CI/CD pipeline 與 K8s 部署環境，實現模型端到端的自動化管理。 • 秉持高標準軟體工程實踐來推動跨團隊協作與交付，與研發及IT 等公司團隊密切配合，確保 AI 解決方案穩定上線。 • 持續評估並導入新技術與工具（如 Opik、Claude Code 等）以引領技術演進，主動推動內部技術分享，建立持續學習的 AI 工程文化。

1. SOC platform 架構與RTL implementation 2. 負責 IP/子模組之 RTL 整合，組成 SoC (System-on-Chip) 或子系統的頂層設計。 3. 依據設計規格，串接不同來源或平台的 RTL，確保各模組間介面相容與功能正確。 4. 撰寫與維護整合 RTL 的頂層模組、配置腳本及連結測試環境。 5. 針對整合後的設計進行功能模擬、靜態時序分析（STA）、Lint、CDC 及等驗證工作，並協助 debug。 6. 與軟硬體、驗證、後端設計等團隊密切合作，確保整合流程順利與產品交付時程。 7. 編寫設計文件及協助設計交付相關事務。

CPU Physical Implementation Engineer Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS. Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP. Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

人工智慧處理器系統架構及RTL設計。 系統架構設計包含效能、功耗、頻寬、以及面積分析。並須負擔RTL開發與部分整合工作。

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and testing skills will be put to good use. Successful handling with many external teams from pre-silicon phase cross to post-silicon on advance silicon and assembly process. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • Product test planning capability: Manage comprehensive post-silicon flow optimization, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications.

Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

1. CPU system design and performance analysis 2. System bus architecture and integration 3. IP and system verification

1. CPU system design, Power, performance and Area analysis 2. MCUSYS u-Architecture design 3. AMBA System bus architecture and integration

1. AI processor subsystem架構與RTL設計 2. AI processor subsystem整合驗證與介面設計 3. AI processor subsystem效能與低功耗設計與分析

The candidate will conduct functional verification of the RF transceiver circuit design at various stages—from individual circuit blocks to the complete system operation—using behavioral models during the design process.

1.AI系統硬體規劃：系統規格與設計需求收集 2.AI系統硬體設計：負責設計和開發硬體系統架構，包括電路設計、元件評估與選擇、客製化元件規劃。 3. AI系統硬體驗證與測試：確認硬體系統正常運作，包含驗證與測試。 4. 跨組織合作：與IC design team、system team、SI/PI team與layout team等等合作，完成系統設計、製作與驗證。 5.客戶與相關廠商支援：包含技術文件撰寫、客戶參考設計支援、on site支援等等。

1. 5G modem 架與數位電路設計 2. CLK, 測試, Reset相關設計與規劃 3. 低功耗設計 4. 系統整合 RTL 到 Gate level, 含STA