交大專區

• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 • HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。

1. Develop and implement DRAM controller/PHY solutions for data-center applications. Validate functionality, improve design to optimize performance, power, latency and efficiency. 2. Memory controller/PHY Integration: Design and integration memory system.

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

1. Develop 3.5D methodology from RTL to GDS and Package 2. Coordinate Thermal and PI/SI team to deal with high power design 3. Execute the project at different phases

1. 高速 SERDES SIPI 分析和整合 2. Core power PI 分析和整合

1. 熟悉 2.5D 或是 3D 封裝技術, 開發和量產經驗 2. 從系統架構優劣比較, SIPI 或是測試或是 thermal 角度來提供適合的封裝技術

•重點開發技術: 系統軟韌體開發、高速資料實體層(physical layer) 資料傳輸軟體開發、優化硬體效能及產品量產品質控管 •主要目標: 完成Enterprise/AI/xPU等相關產業客製化IC的軟韌體開發與系統整合，並協助客戶產品量產 •負責新產品的系統設計與開發，確保符合公司及客戶的需求 •協助量產過程中的技術問題解決，並提供專業建議以提升生產效率與品質 •與跨部門團隊合作，確保產品從設計到量產的順利過渡 •分析並改善現有系統和流程，以提高產品質量和生產效率 •參與產品測試和驗證，確保產品符合相關標準和規範

1. IEEE 802.3 Ethernet PHY & transceiver architecture & algorithm design 2. Digital signal processing of mixed-signal design 3. System simulation/model design for pre-silicon verification 4. System & algorithm design/simulation of high-speed I/F SerDes 5. Make contribution in standard organizations

1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams

1. Develop Ethernet MAC for HPC networking applications. 2. Work closely with architecture, verification and physical teams from specification to implementation.

1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. 2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. 3. Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation.

1. 優化數位 IC 設計 BE 流程與方法 2. 執行與管理數位 IC 設計 BE 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC，例如 CLP 3. 與 FE RTL designer 及 PD APR 團隊密切合作，針對 PPA（Performance, Power, Area）進行 design 及 clock structure 的優化 4. 將依應徵者的年資與專業經驗，提供不同的職級

1. 數位 IC 設計 2. 高速 Ethernet PCS/RSFEC/MAC 設計 3. 高速電路架構與整合

1. New SBT vendor bring up , New SBT vendor YIP , troubleshooting and Ops ​ 2. 3D, 3.5D & e-IVR Technology Enabling, CPC/CPO technology building block development​ 3. Common strip format unification management ​ 4. Advanced PCB Ultra-Large size. I.e., CoWoP, DCAI PCB w/ high layer counts (PCB vendor ISU, GCE, UMTC, VGT ) ​ 5. PCB technology development and DRM owner

1. 與業務使用者進行需求訪談與流程討論 2. IT 相關服務的專案管理 3. 公司商務領域的數位化（應用系統、人工智慧、數據）轉型 1. Engagement and Process Discussion with Business Users. (FIN domain) 2. Project Management on IT Service 3. Digitalization (application, AI, data) Transformation for business domain

1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,品質驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核

Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.

1.Design, develop, and optimize advanced Generative AI models (e.g., LLMs, diffusion models, GANs) for modem system verification and testing. 2.Develop and lead AI-powered tools and platforms to automate software processes, improving efficiency and test coverage in modem system testing. 3.Architect large-scale data pipelines and perform feature engineering and statistical analysis to ensure the quality and integrity of test data. 4.Lead technical projects using Agile methodologies, driving models from PoC to production and ensuring robust testing and CI/CD integration for modem systems. 5.Stay up to date with the latest AI trends, and proactively propose and implement innovations to enhance automation and testing efficiency.

1. 發展多模6G/5G/4G L1/DSP軟體，包含: 狀態機/通道排程/數據機及RF控制 2. 在嵌入式系統實現OFM信號處理機制 3. 熟悉ASIP/DSP架構下的數位通訊

• 領導並參與6G無線通信技術的前沿研究工作。 • 為國際標準組織（如3GPP）制定和完善技術提案。 • 分析新興趨勢，並將前沿概念（如人工智慧、能源效率、衛星通信）納入研究議程。 • 與跨領域團隊合作，評估技術的可行性及其與全球標準的契合度。 • 透過參與全球聯盟、產業論壇及標準化委員會，推動生態系統的互動與參與。 • 指導初級工程師標準化流程及技術寫作。