交大專區

1.回覆客戶技術的問題，提供蝕刻機台技術諮詢。 2.提供客戶處安裝、移機、檢修維護保養機台設備。 3.接聽客戶電話，回應並處理客戶問題、故障排除。 *可接受手機值班&on call。 *願意轉調至其他據點(台中、台南、高雄)。

上下換料,尺寸量測,配合公司完成訂單交付工作,需要對這份工作有熱情且本身要有責任感,歡迎想2度就業或已退休人員加入我們的行列,只要您符合上述條件都將是我們育晟精密需要的人才

1.水電消防配管配線、高低壓電氣設備安裝 2.一般建築物的供水與消防給水管路的簡單基本設計、施工與維護，含污水、排水系統 3.照明燈具、開關插座安裝、火警消防設備安裝、UPS不斷電設備安裝 4.發電機設備安裝、電纜架、匯流銅排設備安裝、電話、對講機設備安裝 意者可電洽(03)5621-351/ 0936385791出先生(廣告勿擾)

1.從事電腦軟體的程式設計、修改、安裝、測試及維護 2.確認軟體程式的目的與功能，進行程序開發及測試，並撰寫軟體程式技術白皮書 3.從事PHP程式開發、管理與維護，及客戶服務與支援 4.客戶教育訓練文件撰寫 5.網站上線後的維護與功能更新 6.PHP網頁系統開發, 前後台皆要會( PHP + APACHE + MS SQL server+ API) 7.PHP需使用8.2.28以上.

1.飯店各項設施之操作、保養及維修等工作(空調、冷凍、水、電、消防、弱電等等)。 2.其他交辦事項。 3.經驗一年以上者優。 4.具有相關證照優。 另有大夜津貼

1. 飯店各項機具設備操作、檢修、維護保養，熟練電氣、給排水、冷凍、空調等專長。 2. 帶領新進技術員示範設備操作、工作程序以及安全程序，進行內部訓練。 3. 主管交辦事項。

熟RTL Design 熟FPGA 開發流程

1. Architecture design and RTL implementation of Smartphone chipset 2. Smartphone SoC and mobile computing platform design 3. System bus and mobile peripheral design, integration, and modeling 4. SoC system performance analysis 5. SoC low power design, integration, and modeling 6. SoC adaptive voltage scaling development

從系統效能，功率消耗，溫度控制...等多重面向分析產品競爭力，進而從系統角度優化硬體架構及軟體控制策略。 Optimize hardware architecture and software control strategy in aspects of system performance/power/thermal to improve MediaTek‘s product competitiveness.

1. 先進 5G 智慧型手機 Modem 設計整合 2. 先進製程 IC Modem 設計實現與技術開發 3. 功耗/效能/面積流程改善開發

1. DSP處理器和相對應的周邊IP驗證環境開發 2. 從module, IP 到system的功能驗證及自動化環境 3. 設計測試pattern以對低耗電及效能做分析 4. Post-silicon 除錯 及 耗電/效能correlation

1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核

We are heavily recruiting talents and professionals in DV, EDA, and AI/ML fields to join our force to conquer new heights in chip complexity! As one of the world’s top IC design companies, MediaTek is constantly pushing the capabilities of chips to the limits. Our newest SoCs and ASICs are wildly sophisticated, packed with industry-leading technologies built by thousands of chip designers. With great design power comes great verification responsibilities. Our team, as a part of the verification force, has put major efforts into creating innovative and robust strategies to fulfill these responsibilities. To ensure high design quality for first silicon success, we have implemented a complete suite of functional and low-power test plans and benches across all design scopes, from IPs to SoC integrations. Furthermore, we have been collaborating with EDA tool providers and academic institutions on leveraging new verification technologies, including emulation, AI tuning, and formal methods, many of which have improved the traditional workflows by orders of magnitude. We also keep challenging ourselves to develop in-house verification tools and platforms to accelerate test regressions and track verification progress more efficiently. All these efforts ultimately lead to our success in delivering high-quality chips over the years.

1. 高速SerDes IP開發 2. 數位電路設計與晶片整合 3. 訊號處理與通訊演算法實現

1. 記憶體電路設計與驗證 2. 記憶體編譯器平台開發

高效能/低成本/低功耗/高效率，具延展性的階層式Smartphone SOC on chip bus 構架設計

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis and post silicon debugging 2. Low power analysis, including pre-silicon power model creation and big data analysis 3. SoC architecture exploration and performance analysis experience is plus

【職缺一】APR實體設計工程師 1. Working on advanced node design methodology, PD execution and sign-off 2. Develop advance clock tree structure 3. Able to handle complex APR with 500+ hardmacros 4. Project analysis in early stage 【職缺二】超大型SoC實體設計工程師 1. executing ultra-large scale SoC hierarchical physical design, in TOP level or GHz complex block level 2. Full experienced PD who can manage/coordinate other PDs‘ various number of hierarchical blocks 3. Flow development experience is a plus, to consolidate ultra-large scale SoC methodologies

對數位電路設計有熱忱者，負責 IP 開發, 整合與偵錯

• 參與3GPP RAN4會議，包括可能的線上或線下討論，以及協助撰寫會議技術文稿 • 檢驗內部及外部標準提案的有效性，透過鏈路級模擬或系統級模擬來撰寫技術文稿 • 於鏈路級模擬或系統級模擬程試中開發新的模組來支援最新3GPP標準的功能 • 參與內部或外部會議，提供想法創意，以及所需之效能評估