清大專區

重要顧客への営業活動・案件フォロー 営業戦略立案、マーケティング活動、海外出張 本社各事業部への報告・連携 望ましい専攻分野：電気電子工学、機械工学（必須ではありません）

工作項目： 1. SDK (Software Development Kit) 驗證/自動化腳本撰寫 2. AI model dataset labeling/ AI benchmark model verification 3. Picture Quality verification 應徵條件： 1. 學士以上，電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程相關科系畢業者為主 2. 熟悉 熟悉C/C++/Python程式語言 3. 具以下經驗者為佳： a.熟悉C/C++/Python程式語言 b.熟悉自動化腳本撰寫如linux shell script經驗者佳 c.熟悉embedded system 開發 (如Android, embedded Linux or RTOS等)經驗者佳

工作項目： Business development manager for ASIC business and account manager for tier-1 US customer 應徵條件： 1. 7 years of experience in sales, marketing, or business development role, at any company in semiconductor-related industry. 2. Strong leadership with excellent written and verbal communication skills in both English and Chinese. Able to work in a multi-geography and cross-functional organization, and engage with technical and non-technical audiences within customer organization. 3. Detailed-oriented; able to work and thrive under ambiguous situation.

Job description : 1. Develop new business with automotive OEM/Tier-1. 2. Key customer relationship management skills up to senior management levels. Qualifications : 1. 5 years of experience in sales, marketing, business development, or any other client-facing role, at any technology firm is a must. 2. Fluent in English is a must. 3. Experience with Automotive car maker or Tier-1 Company is a must. 4. Ability to work in a fast-paced environment with technical and non-technical audiences is a plus. 5. Ability to understand block diagrams of customer‘s systems is a plus. 6. Technical background is a plus. 7. Fluent in Chinese is a plus.

工作項目： 1.網路SDWAN、SASE、Datacenter、OA/OT、Firewall、NPB、WLB、SLB、VPN規劃及資通管理經驗 2.雲端M365、AAD、Teams話務、視訊系統相關規劃及管理經驗 3.微分段、虛擬化(Citrix、VDI、NSX)相關管理與維運 4.資通安全CyberSecurity EDR、NDR、CDR、MFA、MDM等專案規劃執行經驗 5.跨國企業經驗、良好溝通協調能力、勇於嘗試挑戰、接觸新知與運用 6.導入大型專案、能充分團隊協作、自動化機制、合規查核經驗 應徵條件： 1.學士以上，科系不拘 2.熟悉 HPE、Aruba、SASE、MFA、SDWAN、MDR、Citrix、PulseSecure、Qos 3.熟悉 大型網路/系統架構、微分段框架、機房/設備安全、數據中心規劃建置 4.具2年以上企業大型IT架構規劃、責任感和團隊意識、自我激勵具服務熱忱、相關證照及相關經驗者為佳

工作內容： 1.智慧網卡功能及協定之研究 2.制訂智慧網卡產品設計規格 3.IC系統驗證工具開發 4.IC功能Firmware開發 5.FPGA & IC 系統驗證及除錯 6.專案相關報告撰寫 應徵條件： 1.碩士以上電子電機、資訊、通訊工程等相關科技者佳 2.PCIe 相關實作與開發經驗佳 3.熟悉Ethernet 802.3規格佳 4.Ethernet Switch 相關實作與開發經驗佳 5.Linux networking相關實作經驗佳 6.具嵌入式系統開發經驗佳 7.熟悉C語言

工作項目： 1. SoC Bus Acrchitecture planning 2. DDR controller efficiency analysis 3. System bandwidth estimation/analysis and profiling 4. SoC performance emulation. 應徵條件： 1. 碩士以上;電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程等相關科系畢業者 2. 熟悉 Verilog 3. 具3年以上下列相關經驗者佳： (1) 熟悉 SoC bus architecture (2) 熟悉 DDR protocol 以及utilization improvement (3) 有系統效能分析與 memory bandwidth 的經驗 (4) 具有 Zebu或類似之 emulator 整合與驗證經驗

工作內容: 1. Lead and manage all Realtek’s commercial activities including engaging in various stages of the sales cycle, setting up account strategy, executing the account plan, developing multi-level customer relationship across functions of product planning, procurement and senior management, to meet or exceed annual revenue and design targets, along with business objectives for the Southeast Asia and South Asia market. 2. Identify the key client stakeholders and coach those stakeholders to build consensus for Realtek’s solutions within their organization. 3. Clearly articulate customer needs, along with industry trends to Realtek sales management and product lines. 4. Understand the competitive landscape, obtain feedback and work with PMs/engineering teams to improve our offerings to customers. 5. Direct Realtek’s solution strategy for design in efforts during all phase of sales process: device selection, design, prototype, and production. 6. Select and forge alliances with a global set of ODMs/SI partners for Realtek’s entire solution portfolio. 應徵條件: 1. BS in engineering or business required, advance degree (i.e.)MBA/MS desired. 2. 5-10 years of strategic account(OEM/ODM/telecom) sales experience in semiconductor or RF/networking/telecom industry, specifically managing foreign accounts in APAC, Southeast Asia and/or South Asia. 3. Must be fluent in written and spoken English & Chinese. 4. Multi-culture experience is desirable. 5. Must demonstrate ability to address multiple product lines and product segments. 6. Experience and knowledge of key account’s inner organization to work with the influencers, blockers, and decision makers. 7. Ability to present a compelling business case to internal and external constituencies. Able to win support from and effectively communicate to different constituents(sales, engineering, marketing) at different levels. 8. Aptitude to work effectively with ecosystem partners. 9. Capable of thinking out of box and coming up with ideas for giant leaps in growth. 10. Track-record of success in results-driven business development role. 11. Willing to travel when needed(＞30％).

工作項目： 1.負責新廠區整體IT Infra.規劃建置、維運管理，含基礎設施、網路、系統、話務、資通安全等各方面。需獨立應對和解決新建廠區在IT方面遇到的各種挑戰，並確保所有IT服務順利營運 2.遵循總部IT規範，建立並維護新廠區IT Infra.運作流程 3.協調及管理與供應商、承包商間合作，確保IT Infra.設備、服務的及時交付和上線 4.獨立應對新廠區在IT方面遇到的各種問題和突發狀況，良好溝通協調能力，提供使用者端IT技術支援 5.充分與總部IT團隊緊密合作，確保新廠區IT系統與整體架構的整合 應徵條件： 1. 學士以上相關科技畢業者佳 2. 熟悉 HPE、Aruba網管、環控軟體、視訊話務、虛擬化平台、端點偵測及回應 3. 熟悉 大型網路/系統架構、微分段框架、節能機房、設備安全、數據中心規劃維運 4. 具3年以上企業大型IT架構規劃建置經驗、高度責任感和抗壓性、專案管理能力、團隊合作精神、相關證照 相關經驗者為佳

工作內容： 1. 車用產品良率分析、RMA分析、可靠度分析 2. 負責Tape-out相關工作 3. 製程改善相關業務推動 應徵條件： 1. 碩士以上電子電機、材料、物理等相關系所畢業者佳 2. Fab相關工作經驗至少3年以上 3. 熟悉FinFET製程者佳

工作項目： 1. Responsible for product line quality throughout the development phases, from planning to mass production. 2. Product development quality (APQP) assurance including joint reviews, coordinator of quality issues to closure and fan-out. 3. DFMEA assurance. 4. Host continual improvement program and monitor the progress on a regular basis. 5. CAR and RM (risk management) review and tracking. 6. Process audit and action tracking. 7. Project handling. 應徵條件： 1. Bachelor or above of science degree in Electrical/Electronic Engineering. 2. Specialization or related experience in the area of system-level Hardware / Firmware / Software development with a minimum of 5 years of work experience. 3. Experience in project management is a plus. 4. Ability to work independently and in a team-based environment. 5. Good written and verbal communication skills with both customers and internal teams. 6. Experience from 1st tier ODM company is highly preferred. 7. Experience with ASPICE, Functional Safety, Cyber Security is a plus.

職務內容： 1.USB/TBT/HDMI/DP/MIPI...etc 等高速介面規格制定 2.高速介面晶片產品之 晶片架構設計、韌體開發、晶片Silicon驗證 3.高速介面 FPGA 開發 and 驗證驗證 4.高速介面 ASIC 專案開發與設計 應徵條件： 1.碩士以上，電機工程、電控工程、電子工程、自動控制、資訊工程、資訊科學、動力機械相關科系畢業為主 2.熟悉 C、Python、Matlab、Git 3. 具備嵌入式系統開發/學習經驗者，或對 MCU/CPU 架構熟悉者佳 4. 具備基礎數位電路設計 and VLSI 基礎知識者佳 5. 有高速傳輸（不限介面）專業經驗與知識者優先

我們正在尋找嵌入式系統開發工程師加入我們的團隊。如果您熟悉操作系統（OS）或具有OS相關經驗，並且對系統單晶片（SOC）或高階微控制器（MCU）有一定的開發背景，歡迎您申請此職位。這是一個獨特的機會，可以參與先進網路產品的研發，並在車用技術領域有所拓展。 工作項目： 在團隊中參與或負責嵌入式系統的設計、開發和測試。 協助和主導網路產品如交換機（Switch）、路由器（Router）或閘道器（Gateway）的開發流程。 分析和解決開發過程中的技術問題，確保產品的高效性和穩定性。 與跨功能團隊合作，設計和實施符合行業標準的嵌入式程序。 參與車用產品的開發，確保系統的可靠性和安全性。 需求條件： 熟悉或具備操作系統（OS）相關知識和經驗。 具備系統單晶片（SOC）經驗，或有高階微控制器（MCU）的開發背景。 具有網路產品如交換機、路由器或閘道器的開發經驗。 對網路技術有一定的了解，例如TCP/IP協議、網路安全等。 具備車用產品開發經驗者優先考慮。 曾從事NXP或瑞薩（Renesas）MCU/SOC產品開發者將被優先考慮。 優秀的問題解決能力和團隊合作精神。

職務說明： 1. Create formal verification test plan. 2. Develop formal verification environment. 3. Run formal verification and regression, debug failures and analyze coverage. 4. Support other members in deploying formal verification. 5. Survey new formal applications and develop related workflow. 6. Enhance and maintain formal verification workflow. 徵才條件： A. Key qualifications : 1. Master‘s or above in Electrical Engineering, Computer Science. 2. Familiar with standard verification concepts and workflow. 3. Familiar with SystemVerilog and Verilog. 4. Familiar with scripting languages (Perl, Python, etc.). 5. Good communication skills. B. Preferred qualifications : 1. Familiar with SystemVerilog Assertion (SVA). 2. Familiar with formal verification methodology. 3. Familiar with formal tools (JasperGold, VCFormal). 4. Practical experience in formal verification, able to apply strategies to resolve issues during the verification process. 5. Familiar with bus protocol concept (AMBA). 6. Familiar with UVM methodology.

工作項目： 1. 熟悉PADS Layout軟體 2. PCB零件建立與和文件管理歸檔 3. 進行PCB佈局和Layout走線，並生成PCB生產需要的Gerber文件 4. 有PADS Layout相關經驗佳 5. 其他主管交辦工作事項 應徵條件： 工作經驗不拘，有PADS相關layout經驗佳

職務說明： 1. 負責協助公司內部產品開發流程的智慧化與自動化 2. 提升 Digital Design Verification (DV) 的驗證效率與品質 3. 工作常與不同部門協調和討論需求，重視團隊溝通與合作，互相支援提醒 職務內容： 1. 開發與維護前後端系統、資料庫、API、自動化工具 2. 開發維護與內、外部系統工作流 & 資料流的串接 3. 與機器學習工程師及數位設計驗證 (DV) 工程師合作，開發客製化的應用程式或工作流程 職缺需求： 1. 熟悉 PHP、HTML、CSS、jQuery、JavaScript、MySQL 2. 熟悉 PERL 或 Python 3 3. 具 Docker、Kubernetes、Spark、Hadoop、Apache、AirFlow 者尤佳 4. 具備 LLM 觀念與應用開發經驗 5. 具 LangChain、LlamaIndex、vLLM 等 LLM Inference 框架使用經驗者尤佳 6. 具 Vector Database 開發經驗者尤佳 7. 具 AI Agentic Workflow 開發經驗者尤佳 8. 具 SystemVerilog、SVA、UVM、Design Verification 經驗者尤佳 9. 具 MLOps 經驗者尤佳 10. 具問題發現能力、問題分析能力、問題組織能力、問題解決能力、問題追蹤能力、溝通能力 11. Data Science、Data Engineering、Computer Science、Information Engineering、Electrical and Electronic Engineering、Physics 等相關科系畢業者佳 Position Overview: 1. Support the intelligentization and automation of the internal product development processes 2. Enhance the efficiency and quality of Digital Design Verification (DV) 3. Collaborate across departments to address requirements, with emphasis on team communication, cooperation, and mutual support Key Responsibilities: 1. Develop and maintain front-end and back-end systems, databases, APIs, and automation tools 2. Develop and maintain integration with internal and external systems, workflows, and data flows 3. Collaborate with machine learning engineers and digital design verification (DV) engineers to develop customized applications and workflows Qualifications: 1. Proficiency in PHP, HTML, CSS, jQuery, JavaScript, and MySQL 2. Proficiency in PERL or Python 3 3. Strong problem identification, analysis, organization, solving, and tracking abilities, along with excellent communication skills Preferred Qualifications: 1. Experience with Docker, Kubernetes, Spark, Hadoop, Apache, or AirFlow 2. Understanding of LLM concepts and application development 3. Experience with LLM Inference frameworks (LangChain, LlamaIndex, vLLM) 4. Experience with Vector Database development 5. Experience with AI Agentic Workflow development 6. Experience with SystemVerilog, SVA, UVM, or Digital Design Verification (DV) 7. Experience with MLOps Academic Background: Data Science, Data Engineering, Computer Science, Information Engineering, Electrical and Electronic Engineering, or Physics-related fields.

職務說明： 1. 負責協助公司內部產品開發流程的智慧化與自動化 2. 提升 Digital Design Verification (DV) 的驗證效率與品質 3. 工作常與不同部門協調和討論需求，重視團隊溝通與合作，互相支援提醒 職務內容： 1. 將機器學習與人工智慧導入現有的工作流程，並與自動化系統整合 2. 與前端、後端工程師及數位設計驗證 (DV) 工程師合作，開發客製化的 data-driven 應用程式 3. 建構 Data 與 ML Pipeline 4. 開發與維護 ML Model、AI 上線後的性能監測與再訓練 5. 開發與維護 數據清洗、數據串接、數據監控、數據品質管理、Dashboard 6. 設計實驗以評估與分析導入 AI 後帶來的效益 職缺需求： 1. 精通 Python 3 2. 具備 Machine Learning 觀念、任一 ML / DL Framework 3. 具備 LLM 觀念與應用開發經驗 4. 具自行閱讀 AI / ML 論文的能力 5. 具資料科學相關背景，熟悉資料分析、資料視覺化、資料清理、資料處理 6. 具 Time Series Analysis and Forecasting、NLP、DRL、GNN 經驗者尤佳 7. 具 LangChain、LlamaIndex、vLLM、LLaMA Factory 等 LLM Inference 框架與 LLM Fine-tuning 使用經驗者尤佳 8. 具 RAG、Vector Database 開發經驗者尤佳 9. 具 AI Agentic Workflow 開發經驗者尤佳 10. 具 MLOps、MLflow 經驗者尤佳 11. 具 SystemVerilog、SVA、UVM、Design Verification 經驗者尤佳 12. 具問題發現能力、問題分析能力、問題組織能力、問題解決能力、問題追蹤能力、溝通能力 13. Data Science、Data Engineering、Computer Science、Information Engineering、Electrical and Electronic Engineering、Physics 等相關科系畢業者佳 Position Overview: 1. Support the intelligentization and automation of the internal product development processes 2. Enhance the efficiency and quality of Digital Design Verification (DV) 3. Collaborate across departments to address requirements, with emphasis on team communication, cooperation, and mutual support Key Responsibilities: 1. Implement machine learning and artificial intelligence solutions into existing workflows and integrate with automated systems 2. Collaborate with frontend, backend, and digital design verification (DV) engineers to develop customized data-driven applications 3. Construct Data and ML pipelines 4. Develop and maintain ML models, including post-deployment performance monitoring and retraining 5. Develop and maintain systems for data cleaning, integration, monitoring, quality management, and dashboards 6. Design experiments to evaluate and analyze the benefits of AI implementation Qualifications: 1. Expert proficiency in Python 3 2. Strong understanding of Machine Learning concepts and experience with at least one ML/DL framework 3. Knowledge of Large Language Models (LLMs) and experience in LLM application development 4. Ability to independently read and comprehend AI/ML research papers 5. Data science background with expertise in data analysis, visualization, cleaning, and processing 6. Strong problem identification, analysis, organization, solving, and tracking abilities, plus excellent communication skills Preferred Qualifications: 1. Experience with Time Series Analysis and Forecasting, Natural Language Processing (NLP), Deep Reinforcement Learning (DRL), or Graph Neural Networks (GNN) 2. Experience with LLM inference frameworks such as LangChain, LlamaIndex, vLLM, and LLM fine-tuning framework such as LLaMA Factory. 3. Experience with Retrieval-Augmented Generation (RAG) and Vector Database development 4. Experience developing AI Agentic Workflows 5. Experience with MLOps and MLflow 6. Experience with SystemVerilog, SVA, UVM, or Digital Design Verification (DV) Academic Background: Data Science, Data Engineering, Computer Science, Information Engineering, Electrical and Electronic Engineering, or Physics-related fields.

工作內容： 開發生醫感測器及周邊類比電路 徵才條件： 1. 碩士以上，具低雜訊低功耗類比電路設計經驗 2. 有SDM電路經驗尤佳

工作內容： 1. SSD 腳本開發，應用於確保SSD品質，產品類別有NVMe與SATA產品 2. SSD 相關軟體開發，MPTool與支持客戶需求 3. 自動化系統維護與優化 徵才條件： 1.碩士以上資訊相關領域人才 2.具5年以上相關經驗者佳 3.具Linux 以及 windows Driver相關知識者佳 5.具Android與Apple 相關軟體開發經驗者佳 6.具USB驗證經驗者佳

工作項目： Memory Compiler quality verification and support。 應徵條件： 1. 碩士以上; 電機、電子、資工相關科系畢業為主。 2. Familiar with front-end & back-end model including verilog, liberty (nldm/ccs/lvf), dft, redhawk, lef, spice view。 3. Familiar with physical verification flows including drc, erc, lvs, rc extraction。 4. Familiar with Hspice, Spectre, Solido simulation tool & Virtuso, Laker layout tool。 5. Familiar with Scripting language: Python/Verilog/TCL/Shell/Makefile/C。 6. 具以下條件者佳： (1) 熟悉SRAM操作原理及bit cell特性。 (2) 從事SRAM錯誤分析及良率改善。 (3) 具矽智財合約管理經驗。