清大專區

1. CPU功耗分析 (設計 vs. 量測), 確保CPU功耗體質 2. CPU最大電流分析 (設計 vs. 量測), 驗證過電流保護機制確保系統穩定性 3. PMIC+PDN+CPU 功耗效率優化 1. CPU power pre-silicon vs. post-silicon correlation. Ensure CPU power quality 2. CPU max. current pre-silicon vs. post-silicon correlation. Validate max. current protection technique for system stability 3. PMIC+PDN+CPU power efficient optimization

AI Model development, system level modeling and HW/SW system level bottleneck analysis

28nm及以下先進製程(含FinFET) IO電路和ESD防護設計, 工作內容包含 (1) GPIO電路設計(包含ESD/LU防護) (2) 特殊應用IO (SD3.0/SIM card/eMMC等)電路設計(包含ESD/L防護) (3) 高速IO和特殊應用IO在事業部專案上展開和執行 - Advance node (28nm and beyond, including FetFET) IO circuitry and ESD protection design covering fields for (a) General purpose IO circuit design (with ESD/LU protection) (b) Specialty IO (SD3.0/SIM card/eMMC etc.) circuit design (with ESD/LU protection) (c) Project related implementation for high speed/specialty IO Interface - High speed IO, specialty IO circuit design, ESD protection circuit design and simulation. Work with project leader, layout, packaging and system engineers to meet design and system specifications. Work with IO library modeling, characterization teams closely for IP release.

1. 數位設計GAI IDE平台架構需求分析、設計與整合。 2. 數位設計GAI應用開發與測試。 3. 數位設計GAI prompt engineering/RGA/AI-agent框架開發與測試。

1. IC功能驗證 2. IC韌體撰寫(C語言) 3. 協助CSA(Customer SA)/客戶解決問題

1. 著重在高速SerDes IP設計,包括 PCIe/USB的開發、IC功能驗證與系統效能改善 2. 與類比/數位/演算法團隊合作共同開發晶片從雛型設計到量產 3. 負責實作演算法或及相關PHY Link training控制流程設計 4. 在設計階段協助開發團隊建立模擬模型來增加驗證涵蓋率, 並實現自動化驗證高速介面並除錯, 支持IP導入產品與客戶應用

1. 新產品風險評估及擬定封裝顆粒&板級可靠度驗證計畫 2. 驗證失效品之電性及物性分析 3. 客戶新產品可靠度問題諮詢 4. 新封裝供應商稽核及認證 5. 封裝供應商品質及可靠度管理 (品質異常事件處理, 變更管理, 例行性稽核, 評比等) 6. 新產品及技術導入品質及可靠度管理 7. 封裝供應商品質改善專案

相機影像調適方式優化工程師 1. ISP/3A 參數調教. 2. 改善調適流程以及方法. 3. 改善調適前置軟硬體檢查流程 4. 改善調適工具使用效率

1. LCD Monitor IC相關的韌體開發 2. 影像處理相關應用與支援客戶產品開發 3. LCD Monitor UI與周邊相關應用的開發 4. 可配合出差

Analog/Mixed-signal circuit design

Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.

1. 具備先進製程SoC 晶片 top flow 的專業知識。 2. Advance CTS design 3. 開發先進制程的 Power Mesh 經驗。

1. Work on 7nm~3nm physical design implementation, methodology, and sign-off 2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. IC 整合 2. Package/Floorplan 整合

Do you want to be part of a smart and passionate team of researchers, advancing artificial intelligence to the next level of end-user experience in their daily lives? MediaTek Research Taiwan is seeking driven and brilliant young students to join our efforts by providing Internship placements. We are currently working on Natural Language Processing, AI for Chip Design and more! We hope you can join us as we embark on the a journey from research to product! The ideal candidate is open-minded, passionate about realizing AI in practical use cases, and looks forward to cutting-edge challenging problems. • You have experience on Frontend/Backend/Full-Stack Web programming • You have basic understanding of the foundations and engineering aspects of AI, hands on experience with machine Learning frameworks (PyTorch, Tensorflow, JAX) is a plus. • You are a proficient scientific communicator. You are committed to your goals and working in a team. • You are eager to tackle real-world applications with state of the art methodologies. We want your ideas to shine! As an Engineering Intern in our team, you will collaborate with our researchers and worldwide colleagues and develop applications and algorithms that make a real difference in everyday devices. Your developments would significantly enhance the experience of numerous end users across our product range.

1. 5G 物理層/通訊協定規格及流程驗證 2. 熟悉5G L1 phy, 通訊協定, IMS, GCF/PTCRB, RF conformance , 並設計測項保證手機系統品質及效能 3. 5G R16 and later features and later new feature verification 4. Maximum throughput 測項開發及驗證 5. 5G 系統環境模擬及測項開發 6. 與營運商或基地台廠商執行互操作聯調/互操作測試/場測 7. 自動化工具開發及大數據通訊協定分析

Develop advanced package technologies for MediaTek‘s HPC business

1.自動化5G環境模擬工具開發 2.protocol 或 效能問題的分析與模擬系統設計 3. 5G system 系統驗證 與modem效能benchmark 與 系統穩定性監控 4.對 IOT/field test and protocol debug 有相關經驗尤佳

1. 智慧型手機系統記憶體與儲存: DRAM (LPDDR4, LPDDR5, LPDDR6...) / Storage (UFS, eMMC...)驗証 2. 系統驗証方法研究與開發 3. 規畫驗証計畫 (test plan, test case) 4. 自動化測試環境開發

1) 開發針對本公司類比晶片設計所使用的EDA工具或CAD設計流程,工作內容包含:需求分析,演算法設計,資料處裡,與使用者介面設計 2) 推廣與嵌入新的流程到未來開案的晶片,目標是提升晶片開發的效率與品質 3) 透過設計演算法或以AI技術來定義與解決IC設計流程遇到的難題 4) 研究與探求最佳的類比設計流程(前後段)