交大專區

1. 測試整合工程師 2. PKG 整合工程師

1. USB3 Controller Maintainess/Development 2. Short term =＞ Handle the USB3 Controller for different projects and adding new features. Long term =＞ Co-work with USB4 team to co-develop the next gen USB4 controller

• 主導 6G 頻譜接取（spectrum access）、初始接取（initial access）、能源效率（energy efficiency）或 MIMO 等技術的開發與 3GPP 標準化，推動功能從概念落實至正式核定的規格。 • 在 3GPP 及其他標準組織中撰寫並推動技術提案（contributions），並凝聚共識以促成其採納。 • 爭取並擔任 3GPP 關鍵領導職位——包含 feature lead 與 rapporteur——並代表公司策略性競選。 • 跨 3GPP 各工作組（working groups），以及在標準化團隊與產品實現團隊之間進行協作，確保技術可行性與設計一致性。 • 指導資淺工程師熟悉標準化流程與技術開發。

- This position is for an SoC Architect, responsible for evaluating the technical feasibility and architectural direction of new products prior to project kickoff. - The role requires close collaboration with business teams to clarify market needs and product requirements, as well as cooperation with engineering teams to explore the competitiveness and feasibility of various SoC architecture options. - The architect will integrate cross-functional inputs to define the optimal system-on-chip design architecture, serving as the foundation for subsequent product development. - 此職缺為 SoC Architect，負責於專案啟動前進行產品的技術可行性與架構方向評估。 - 需與商務單位合作，釐清市場需求與產品規格；並與各工程團隊協作，探索不同 SoC 架構方案的優劣與競爭力，評估技術風險與可行性。 - 最終需整合跨部門意見，制定最佳化的系統晶片設計架構，作為後續產品開發的基礎。

1. 用電設備檢驗維護，負責協助管理維護客戶電力設備 2. 檢測缺失估價及檢測報告整理 3. 各種緊急事故搶修 4. 客戶電價分析說明 5. 用電設備疑慮解答

車用電源系統，車用電子，12V or 48 V 等產品的系統電源設計/驗證之電源應用工程師，需與Designer 、PM、SW 等單位討論系統的電源設計的競爭力的分析，並驗證系統Power solution，撰寫design note 等文件，協助處理客戶開案並量產的相關系統電源問題。

1. Chip integration and quality check 2. DFT insertion, verification and scan coverage analysis 3. Synthesis and PPA analysis

Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.

- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. - Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. - Create and execute verification test plans, focusing on functional coverage. - Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. - Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. - Support performance verification, emulation, data collection, debugging, and PPA improvements. - Conduct formal verification.

Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting

Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis 2. Basic knowledge of analog design 3. Mixed signal design experience is a plus. 4. SoC architecture exploration and performance analysis experience is plus. 5. Post-silicon mass production experience ((Ex: DFT, CP, FT)) is a plus. 1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 2 . 具類比IC設計的基本知識 3. 混和訊號IC設計經驗是加分項 4 . 系統架構分析經驗是加分項 5 . 具IC量產相關經驗(Ex: DFT, CP, FT)是加分項

We are looking for talented engineers to join our GPU Architecture team. In this role, you will be at the forefront of defining the next generation of mobile high-performance GPUs. You will be responsible for developing a C++ based model, which serves as the primary tool for architectural exploration, bottleneck analysis, and performance projection before silicon availability. Whether you are a fresh graduate with a strong passion for computer architecture or a seasoned veteran in performance modeling, we invite you to help us push the boundaries of graphics rendering and compute efficiency.

1. 負責CP/FT/SLT/Burn-in/Socket 測試配件開發與驗證 2. 先進封裝測試配件新技術新需求開並導入量產 3. 測試配件供應商管理

1. 公司各類資訊系統開發與維護 2. 網頁管理維護更新 3. 電腦及週邊設備之操作、查修與管理 4. 其他主管主管交辦事項

1.俱水電 機電工程等專案管理經驗者 2.各種電力緊急事故搶修 3.熟客戶需求之估價報價 4.協助電檢維護高低壓保養檢測 5.客戶缺失改善工程 6.熟悉工程業務相關之內外作業及現場管理經驗者 7.指揮管理，以控制工程的執行進度與施工品質。 8.公司交辦事項

1.軟體規劃製作。 2.自動控制產品規劃、設計、監控。 3.電氣工程系統規劃、設計、監控，程式設計。 4.負責自動化設備、系統介面之維護及改善。 5.負責自動化系統各類規範與相關文件之撰寫、修改。

1. 管理 IT 團隊日常運作，建立並落實標準化流程 2. 規劃與優化資訊系統架構、系統整合與資安防護 3. 主導或參與 ERP 等大型資訊專案 4. 執行 IT 專案管理 5. 跨部門溝通協調，整合需求並提供系統解決方案 本職務為公司關鍵支援角色，能實際參與核心系統與流程優化，對企業營運具實質影響。

1.高壓、低壓之電力儀電(變電)設備、發電機、消防等之定期檢測、維護、保養、維修 2. 電力、發電機、消防巡檢，其他客戶要求巡檢保養項目 3.各種緊急事故搶修 4.各種檢測報告書整理審核 5.支援工程維護課施工 6.客戶缺失改善工程 7.客戶需求之估價報價 8.客戶電價分析說明報告 9.用電設備疑慮解答 10.熟悉工程業務相關之內外作業及現場管理經驗者 11.指揮管理，以控制工程的執行進度與施工品質。 12.工程專案管理經驗者 13.公司交辦事項

1. 高壓、低壓之電力儀電(變電)設備、發電機、消防等之定期檢測、維護、保養、維修 2. 電力、發電機、消防巡檢，其他客戶要求巡檢保養項目 3.各種緊急事故搶修 4.各種檢測報告書整理 5.支援工程維護課施工 6.客戶缺失改善工程 7.客戶需求之估價報價 8.客戶電價分析說明報告 9.用電設備疑慮解答