清大專區

The Senior Power Integrity Engineer is responsible for the design and analysis of Power Delivery Networks (PDNs), encompassing voltage regulators, PCBs, substrates, and silicon dies, to drive strategic technology development for data center SoCs. Key responsibilities include conducting power integrity pathfinding, developing both detailed and reduced-order PDN models, and optimizing PDN performance through comprehensive time-domain and frequency-domain analysis. This role requires proficiency in scripting and design automation, as well as expertise in analytical methods and commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and generate accurate N-port models.

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

1. 負責高速 Serdes相關開發, 包含驗證, 客戶支援 (熟悉架構, 韌體、除錯、優化及測試等工作項目) 2. 開發測試自動化 3. 協同團隊共同完成系統雛型建立及性能優化與調適 4. 達成客戶端產品導入，並支援產品量產

1. 應用於I/O 小晶片的 SerDes 設計驗證工作. 包含從原型測試到量產晶片, 並與類比, 數位和演算法設計團隊合作. 2. 負責實現 SerDes 韌體設計, 以驗證連線效能和實現量產測試 3. 負責建立自動測試和資料分析, 以測試SerDes的晶片特性和分析失效晶片

* 資深SI/PI工程師 * 封裝/電路板 SI/PI設計與晶片開發於消費型產品, 車用以及企業級高效運算產品 * 記憶體以及高速Serdes SI/PI設計 * 高效能CPU/GPU/APU PI以及PDN設計 * 建立封裝/電路板的高速序號設計準則, PDN電氣規格, 以利產品進行

1. 高速 SERDES SIPI 分析和整合 2. Core power PI 分析和整合

先進封裝技術開發 1. 先進新產品導入技術開發 (新產片試產規劃, DRC/DRM檢驗, DOE及良率改善規劃, 量產區間及良率分析) 2. 熟悉先進chiplet及3DIC封裝技術開發 3. 晶圓級與面板級先進封裝結構設計

1) 建立車用cockpit/ADAS等ECU系統級熱模型，並設計具市場競爭力的散熱解決方案。 2) 參與制定、分析、評測SOC TDP(Thermal Design Power) 3) 設計、設置、執行並交付各種thermal和TDP實驗的結果，驗證SOC 和系統硬體性能。 4) 針對下一代車用晶片，規劃熱管理方案，並參與制定晶片及系統的thermal/power設計需求 5) 管理技術專案，並與其他內部組織和客戶合作，支援開發週期中的執行過程。 6) 執行熱模擬和驗證，並與合作單位展示和溝通成果

【About the Role】 Join our cutting-edge team to shape the future of communication technologies. As a key member of our engineering team, you will be at the forefront of developing innovative baseband algorithms, designing robust Ethernet or PCIe/USB4 PHY systems. Your expertise will drive the creation of low-power, high-speed communication systems and advance the digital signal processing of mixed-signal systems. Additionally, you will play a pivotal role in representing our company at IEEE/OIF standard meetings, influencing the future of communication standards. With the rapid advancement of Generative AI, the demand for high-speed Serializer/Deserializer (SerDes) in data center applications is skyrocketing. This trend presents significant business opportunities, and you will be instrumental in capitalizing on these developments. 【Key Responsibilities】 1. Develop state-of-the-art baseband algorithms to enhance communication system performance. 2. Architect and design Ethernet or PCIe/USB4 PHY systems, focusing on system efficiency and reliability. 3. Lead communication system verification efforts to ensure system integrity and performance. 4. Innovate in architecture and algorithm design for low-power, high-speed communication systems. 5. Apply digital signal processing techniques to optimize mixed-signal system functionality. 6. Actively participate in IEEE/OIF standard meetings, contributing to the development of industry standards. 7. Leverage the trend of Generative AI to drive the development of high-speed SerDes solutions for data center applications.

1.AI系統硬體規劃：系統規格與設計需求收集 2.AI系統硬體設計：負責設計和開發硬體系統架構，包括電路設計、元件評估與選擇、客製化元件規劃。 3. AI系統硬體驗證與測試：確認硬體系統正常運作，包含驗證與測試。 4. 跨組織合作：與IC design team、system team、SI/PI team與layout team等等合作，完成系統設計、製作與驗證。 5.客戶與相關廠商支援：包含技術文件撰寫、客戶參考設計支援、on site支援等等。

1. Serdes/High speed interface related PHYD IP architecture planning. 2. Serdes/High speed interface related PHYD IP RTL coding. 3. Serdes/High speed interface related PHYD IP front-end and back-end integration. 4. Co-work with MAC design team and DV team for IP verification. 5. Co-work with Analog design team for PHY co-simulation.

1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams

1. Develop Die-to-die and UCIe digital IP for HPC SOC. 2. Integration of D2D controller and PHY to timing closure and DFT. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.

1. 數位 IC 設計 2. 高速 Ethernet PCS/RSFEC/MAC 設計 3. 高速電路架構與整合

1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. 2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. 3. Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation.

1. HSI IP development 2. Short term: Help integration of on-going project including QC. 3. Long term: Deep learn into 3rd party HSI IP. Know the detailed spec of PCIe/UCIE/USB4 and able to co-work with DV.

1. 設計、開發和維護多媒體應用程式，包括但不限於Video playback, Image, playback。 2. 開發和優化 Android 平台上的多媒體應用程式，確保其性能和穩定性。 3. 開發和維護嵌入式系統上的多媒體應用程式，確保其在資源受限環境中的高效運行。 4. 與設計師、產品經理和其他工程師合作，確保多媒體應用程式的功能和使用者體驗達到高標準。 5. 進行多媒體技術的研究和創新，持續改進現有產品的性能和功能。 6. 撰寫和維護技術文件，確保程式碼的可讀性和可維護性。 7. 參與產品測試和除錯，確保產品的穩定性和可靠性。 8. 依據市場需求和用戶反饋，進行產品的優化和升級。

1. 產品品質問題電性 / 物性分析 2. 產品測試機台操作和測試分析 3. 跨部門溝通以分析產品故障真因

1) 軟體層面的 Android 系統整合 2) Linux 系統軟體開發 3) Linux Kernel Driver開發

1. Processor core, cache and peripheral verification 2. Verification flow and methodology 3. Advanced tool and verification technology survey