交大專區

1. Wi-Fi 驅動程式和韌體開發設計及驗證 2. Wi-Fi 等無線晶片之跨層架構介面設計 3. 開發並取得Wi-Fi Alliance認証 4. 移植WLAN驅動程式到各Android, Linux核心和手機產品 5. 協助研發軟體新技術與新工具 6. 維護量產的產品

1. Clock架構與RTL設計 2. SOC IOMUX架構與RTL設計 3. SoC Floorplan架構規劃 4. 旗艦智慧型手機晶片整合 5. 車用系統晶片整合

1. CPU system design and performance analysis 2. System bus architecture and integration 3. IP and system verification

無線網通晶片設計/整合/驗證

1. 運算架構開發研究與競爭分析 2. 系統單晶片的軟硬體行為之 效能/功耗 分析與最佳化 3. CPU/GPU/NPU系統模型設計與開發

1. AI處理器和相對應周邊IP/系統驗證環境開發 2. 從IP到系統的功能驗證和自動化環境 3. 開發低耗電和效能的測試 4. post-sillicon除錯 5. emulator 環境建立

1. 設計 5G/B5G 和新一代多模通訊協定架構，開發具有超高數據速率、低延遲和出色用戶體驗的通訊協定軟體，以廣泛運用在手機、人工智慧物聯網和車用系統上。 2. 與全球領先網路設備商（如：華為、中興、愛立信、諾基亞）進行互操作開發測試，以早期達成產品相容性目標。 3. 開發領先全球的網路運營商功能，與世界頂尖客戶合作，實現新一代出色的移動通訊產品。

解讀客戶的網絡安全需求 從網絡安全需求中推導出功能和安全概念 制定和審查安全系統架構 與 IP 團隊和客戶溝通和協調安全設計 執行系統安全分析（例如：TARA）

解讀客戶的網絡安全需求 從網絡安全需求中推導出功能和安全概念 制定和審查安全系統架構 與 IP 團隊和客戶溝通和協調安全設計 執行系統安全分析（例如：TARA）

1. 旗艦智慧型手機晶片整合 2. 車用系統晶片整合 3. Clock架構 4. Timing收斂與分析 5. DFT/Test mode整合驗證

1.CPO SERDES 系統開發​ 2.CPO Optical系統開發

1.PCB power related hardware design：Resonsible for design and develop hardware including circuit design, component evaluation and selection, customized component planning, layout review, etc. 2. System specification and design requirement collection. 3. System hardware verification and testing: function verification and power quality measurement. 4. Cross-organizational collaboration: Collaborate with IC design team, system team, SI/PI team, layout team, etc. to complete system design, production and verification. 5. Customer and related manufacturer support: including technical document writing, customer reference design support, on site support, etc.

1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams

1. 優化數位 IC 設計 BE 流程與方法 2. 執行與管理數位 IC 設計 BE 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC，例如 CLP 3. 與 FE RTL designer 及 PD APR 團隊密切合作，針對 PPA（Performance, Power, Area）進行 design 及 clock structure 的優化 4. 將依應徵者的年資與專業經驗，提供不同的職級

1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,品質驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核

1. Define power states and management hardware architecture for optimal power performance. 2. Design microprocessor-based power management controller and HW assistance designs. 3. Define power architecture by performing power rail tradeoff analysis with adaptive voltage scaling consideration

1. Develop scalable platform clocking architecture for automotive SoC 2. Enhance SoC clock architecture and technology development to address the automotive SoC requirements 3. Drive clock architecture and designs to optimize power, performance, and implementation, including physical design and timing closure

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

• Define GPU compiler software architecture and interfaces. • Development/implement GPU compiler pipeline, linking and various optimizations/transformations. • Collaborate with Driver team, HW team to implement new API & HW features. • Collaborate with Driver team, HW team to improve/tune performance & power consumption. • Execute & deliver to meet milestones/schedules. • Analyze and debug code generation issues. • Construct reliable & trustable relationships across teams internally & externally.

Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products. • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. • Document on new flows and processes for AMS DV. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA