交大專區

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and testing skills will be put to good use. Successful handling with many external teams from pre-silicon phase cross to post-silicon on advance silicon and assembly process. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • Product test planning capability: Manage comprehensive post-silicon flow optimization, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications.

We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

1. Familiar with DFT plan, methodology, implementation 2. Familiar with new DFT flow such as SSN, HSIO 3. Familar with STA, timing analysis

- 透過推動跨部門在技術需求、介面定義與交付項目上的一致性，協調先進封裝解決方案的開發（例如 CoWoS、2.5D/3.5D 整合，以及 Chiplet 架構）。 - 主導 SoC Floorplanning 以最佳化 PPA（功耗、效能與晶片面積），並在時序收斂、繞線壅塞、電源域邊界，以及 PDN／熱設計等考量間取得平衡。 - 與封裝團隊合作制定並優化 Ball/Bump 配置（bump/ball map），以滿足 SI/PI、電流承載能力、可製造性與可靠度等需求。

如果你是一位熱愛研究新技術、對自我產出要求極高並有良好的團隊合作精神的工程師，那我們誠摯地邀請你加入我們！ 身為前端工程師，加入後你將會與其他研發團隊夥伴密切配合，開發出高度使用者友善的網站。 根據不同專案，裡面有用到 Next.js、React.js、TypeScript 等，你將會負責線上產品的維護與新專案開發，你能使用到最新的技術，持續學習和成長，並為我們的客戶持續提供更好的網站體驗。 【工作內容】 - 線上產品維護迭代。 - 實作需求並與 PM、UI 設計師等進行可行性評估。 - 協助新技術拓荒與技術導入評估。 - 優化現有程式架構、網站效能。 - 熟悉 API 串接與使用。 【職務要求】 - 具備一年以上前端網站開發經驗。 - 熟悉 React.js (16.8+) 、Next.js (12+)，能熟練 hooks 的使用。 - 熟悉JavaScript ES6 特性及語法，懂得善用各種 node 套件進行開發。 - 熟悉或能使用 TypeScript 進行強行別開發。 - 熟悉 Git 版本控制。 - 熟悉 RESTful API 並有 API 串接實務經驗。 - 能夠掌握開發時程，確保交付品質。

1. 熟悉內部稽核、內部控制、風險管理或資訊系統稽核基本方法，能將流程風險轉化為可測試的控制點與稽核程序。 2. 具備 IC 設計、半導體、電子產品研發或軟硬體開發流程之基本理解，了解從需求、設計、驗證、release 到量產維護之流程風險。 3. 熟悉研發流程常見控制，例如 design review、code review、branch protection、bug tracking、coverage review、waiver approval、release gate、tape-out sign-off 等。 4. 具備資料分析能力，能使用 SQL、Python、Excel Power Query、Power BI、Tableau 或其他資料分析工具進行資料清理、比對、例外偵測與視覺化。 5. 能理解並分析研發系統資料，例如 Git / GitLab / GitHub、Jira、bug tracking system、PLM、release system、IAM、HRIS、EDA / CAD flow log 或其他工程資料。 6. 具備權限管理與存取控制概念，理解 least privilege、JML access control、privileged account review、terminated user access removal、role-based access control 等控制。 7. 了解資訊安全與資料保護基本概念，包括 DLP、USB / cloud storage control、source code protection、sensitive data classification、audit trail、log review 等。 8. 了解智慧財產權與研發資料保護風險，例如 High Sensitive IP、third-party IP、open source software、SBOM、EDA / PDK / Foundry data、NDA data、export control 等。 9. 具備流程訪談與跨部門溝通能力，能與 RD、IT、資安、資料治理、法務、專案管理及流程 Owner 討論風險、控制、資料來源與改善方案。 10. 具備將業務問題轉換為資料規則的能力，例如將「未完成 code review 即 release」轉換為 commit、PR、approval、release tag 之間的資料比對邏輯。 11. 對 AI、Agent、RPA 或自動化稽核工具有興趣或實務經驗，能協助規劃 Audit Agent 的測試規則、資料需求、輸出格式與人工覆核流程。 12. 具備良好文件撰寫能力，能撰寫稽核底稿、流程圖、風險控制矩陣、缺失描述、根本原因分析、改善建議與管理階層報告。 13. 具備獨立思考、問題分析與專案管理能力，能同時處理多項稽核任務、資料分析需求、缺失追蹤與跨單位溝通。 14. 具備高度職業道德、保密意識與風險敏感度，能審慎處理研發機密、客戶資料、IP 資料、權限資料與稽核發現。

1. CPU system design and performance analysis 2. System bus architecture and integration 3. IP and system verification

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification.

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications • Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements • Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement • Location: Hsinchu, Taipei, Singapore, USA

We are looking for a highly skilled DFT CAD and Methodology Expert to develop and deploy advanced test methodologies for next-generation data center and AI ASIC. Enhancing the efficiency and quality of our ASIC development and testing procedures. The successful candidate will work within the CAD team to innovate test solutions for complex 2.5D/3DIC, ensuring high quality and yield for advanced packaging technologies. Key Responsibilities • Methodology Development: Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST (MBIST). • Tool Automation: Create scripts (Python, TCL, Perl) to enhance and automate DFT flows, accelerating simulation runtimes and improving quality of results (QOR). • EDA Tool Integration: Collaborate with EDA vendors to enhance tools for advanced packaging, including test verification and pattern generation. • Support & Debug: Support DFT integration teams with CAD flow issues, debug complex issues, and provide technical mentorship. • 3DIC/2.5D Expertise: Develop and implement testing strategies for chiplets and TSV-based 3D stacks. • Location: Hsinchu, Taipei, Singapore.

At MediaTek, we are at the forefront of enabling device + cloud hybrid architectures for generative AI. On-device AI offers significant advantages, including low latency, enhanced security, privacy, and personalization through fine-tuning to meet specific user needs. As an AI SDK/IDE Software Engineer, you will be responsible for developing and enhancing our NeuroPilot SDK workflow. This role involves designing and implementing features that support neural network development stages, including network conversion, optimization tuning, profiling and accuracy analysis. You will work closely with cross-functional teams to ensure a seamless user experience and robust functionality. We are seeking talented individuals to join our team and contribute to this cutting-edge field.

0. 基本英文文書能力 1. Responsible for establishing and improving software engineering relevant systems and automation mechanism 2. Responsible for improving software configuration management systems 3. Responsible for improving release automation systems 4. Responsible for improving Linux build environment

1.AI系統硬體規劃：系統規格與設計需求收集 2.AI系統硬體設計：負責設計和開發硬體系統架構，包括電路設計、元件評估與選擇、客製化元件規劃。 3. AI系統硬體驗證與測試：確認硬體系統正常運作，包含驗證與測試。 4. 跨組織合作：與IC design team、system team、SI/PI team與layout team等等合作，完成系統設計、製作與驗證。 5.客戶與相關廠商支援：包含技術文件撰寫、客戶參考設計支援、on site支援等等。

您是否對智慧機器人、物聯網與自動化系統充滿興趣？我們正在打造下一代 AMR 車隊管理與智慧工廠平台（FMS / IoT Platform），讓機器人、設備與雲端系統能夠即時協同運作。 在這個角色中，您將負責核心平台後端系統的設計與開發，並與 ROS-based 機器人系統深度整合，實現任務派送、狀態回傳與即時控制。 您將參與： * IoT 與機器人資料流平台設計 * FMS（Fleet Management System）核心後端開發 * 與 ROS2 系統進行通訊與整合 * 建構可擴展、高可靠性的工業級平台架構 我們希望這不只是寫程式，而是一起打造「讓機器人真正運作的系統」。 工作內容 * 負責 FMS / IoT 平台後端系統設計與開發 * 設計與開發 RESTful API、WebSocket 即時通訊服務 * 與 ROS / ROS2 機器人系統進行資料與指令整合 * 建立設備、任務、地圖與車隊管理核心模組 * 整合 MQTT / IoT 通訊架構 * 優化系統效能、穩定性與可擴展性 * 與前端、ROS、韌體與演算法團隊協作 我們期待的人 * 對機器人、自動化與智慧系統有熱情 * 喜歡處理「真實世界系統問題」（不是純 Web） * 能與 ROS / 軟體 / 硬體跨域合作 * 具備系統思維與架構能力 * 願意深入理解機器人如何運作

【景碩科技最新廠，擴建廠需求，歡迎嚮往管理職發展的夥伴加入景碩】 1.先進封裝製程擴建及設備自動化連線串接。 2.全新生產製程導入規劃。 3.評估最適化之產品生產流程，制定製造程序及標準，提升製程良率及改善報廢。 4.先進封裝製程標準作業規範制定。 5.設備製程品質監控及預警系統建立。 【求職Q&A，您的疑慮，景碩先來幫您回答】 Q1:公司有提供宿舍嗎? A1:針對外縣市同仁或是居住地離公司25公里以上者，提供便利實惠套/雅房員工宿舍，每月僅需支付1200-1500元(依房型而定)，讓外縣市員工免煩惱，一卡皮箱即可輕鬆入住! *目前宿舍安排於桃園新屋廠區周邊，距幼獅廠約20分鐘左右車程，需自備交通工具代步。 *或可申請租屋補貼，可享有每月$4000元補助。 Q2:公司附近交通便利嗎? A2:幼獅廠周邊具幼獅交流道；幼獅廠距楊梅市區約5分鐘車程，距埔心市區約10分鐘車程，可輕鬆抵達楊梅或埔心鬧區。 Q3:面試前須準備什麼? A3:帶著一顆熱忱的心及優質的工作態度，讓景碩與您一同成長茁壯!!

1) 軟體層面的 Android 系統整合 2) Linux 系統軟體開發 3) Linux Kernel Driver開發

我們正在尋找一位資深軟體品質保證工程師（Senior SQA Engineer）加入我們的團隊，負責為汽車系統提供高品質的驗證工作。您將設計並執行測試計劃，驗證系統設計和架構的需求，並協助確保系統的穩定性與效能。這個職位將有機會與全球一級供應商（Tier-1 suppliers）及車廠（OEMs）合作，參與新一代汽車系統的開發，並在一個協作且創新的工程環境中工作。 主要職責 1、為 Tier-1 Hypervisor 平台上的 Yocto Linux 和 Android Automotive OS 虛擬機（VM）制定並執行測試計劃。 2、驗證汽車平台的功能、效能及穩定性。 3、與跨部門團隊合作，定義測試範圍、驗收標準及風險管理。 4、撰寫詳細的測試報告，並提供可行的回饋以提升產品品質。

類比、射頻、3D-IC矽中介層等電路全客製化佈局設計及自動化流程設計

1. Responsible for high-speed UCIE development, including architecture definition, verification, and customer support (familiar with architecture, firmware, debugging, optimization, and testing tasks). 2. Define architecture and specifications through simulations. ( Matlab ) 3. Develop test automation. 4. Collaborate with the team to establish system prototypes and optimize performance. 5. Achieve product integration for clients and support mass production.

1. 負責CP/FT/SLT/Burn-in/Socket 測試配件開發與驗證 2. 先進封裝測試配件新技術新需求開並導入量產 3. 測試配件供應商管理