交大專區

1. Computing technology roadmap planning and management. 2. Key customer/3rd party/industrial leader partnership management 3. Gaming ecosystem engagement

1. SoC chip integration from RTL to gate level including timing closure and testability 2. Design methodology and integration flow improvement

• Cellular ECO system夥伴關係 • Cellular modem新技術分析與市場技術走向分析 • Cellular ECO system engagement and partnership • Cellular modem new technology investigation and technical marketing

1. 5G modem platform架構設計及相關數位電路設計 2. 整體晶片之clock, reset, bus, 測試模式, 低功耗模式之規劃及設計 3. 由RTL到gate level的platform整合工作, 包含timing收斂及可測試性設計 4. 設計方法及整合流程的改進

1. 先進 5G 智慧型手機 SoC 設計整合 2. 先進製程 IC 設計實現與技術開發 3. 關鍵 IP Modem, DRAMC, ISP RTL-2-GDS technology development

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1.數位晶片設計流程與整合, 包含timing收斂與DFT 2.數位設計流程整合與QC流程優化

This position will be involved in the design methodology development with Foundry and EDA in leading-edge process node: 1. Will work extensively with micro-architects to make best-in-class performance/power/area 2. Will drive RTL-to-GDS flow through synthesis and place-and-route to achieve competitive targets for performance/power/area 3. Will work with multi-functional engineering team to implement and validate physical design on the aspects of timing, power, area, reliability, and test-ability

1) Manage and develop in-house design automation programs 2) Analyze and summarize memory usage profiling 3) Benchmark 3rd party memory IP 4) Co-work with circuit designer for memory compiler development 5) Other technical task assigned from manager

1. 資深SI/PI工程師 2. 晶片開發, PDN/IR分析 3. DDR 介面SI/PI設計 4. 高速Serdes 介面SI/PI設計 5. 客戶技術支持

1. 系統單晶片DFT架構規劃與設計 2. 負責與客戶討論DFT架構，並開發對應的DFT流程 3. Scan/DFT電路設計timing收斂 4. DRC偵錯與DFT設計模擬 5. 測試涵蓋率的改善 6. ATPG pattern產生，偵錯，與量產管理

1. Build-up methodology for SoC system-level modeling and emulation platform (ex. Zebu, PXP) 2. Analyze GPU benchmarks and critical game applications, identify performance bottlenecks from computing system level and provide HW/SW optimizations 3. Explore the best-fit computing system architecture for next generation IP and SoC

1. PMIC/SerDes 電路驗證 2. 類比電路驗證方法流程開發 3. Serdes/類比/RF電路之IR/EM 分析 4. 類比電路 Verilog-A 行為模型開發 5. 晶片-封裝 (WLCSP/CoWoS/3DIC/InFO 3D.)IR/EM 協同分析流程開發 6. 類比/射頻 CPM 模型化

職責說明: 1. 提供Whole-Chip Memory(SRAM,TCAM), 的最佳選擇方式(PPA), 根據不同先進製程 2. 內部或外部客戶溝通討論出optimized Memory PPA solution, 相關周邊邏輯電路設計, 以及測試架構(MBIST)與方法. 3. Whole Chip MBIST 架構設計與實現 4. 協助Memory相關的Timing closure以及 IR 改善方案. 5. MBIST 量產測試相關工作, 除錯以及良率提升. 6. 對先進製程Memory特性的深入理解, 提出應用於ethernet, AI, Cloud, 5G Infrastructure 的適合解決方案.

AS deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. -SHBG DV is in charge of development and implementation of TV, monitor and smart home product line verification plan. -It included: integrated simulation/verification env development, BUS fabric verification, Serdes IP verification, and architecture explore by ESL. -Need to leverage the latest EDA tool and concept to accomplish the verification plan

1. 訂定DFT plan 及執行 DFT/ATPG相關任務 2. 協助改善ATPG效率 3. 提供量產ATPG pattern 及協助量產階段除錯

專案管理 客戶夥伴關係 客戶工程技術支持 (4G/5G modem/protocol/system)

802.11無線網路協定與驅動開發

高速通訊系統的演算法與架構設計(USB/DP/HDMI/SerDes)

1. 研究IP開發測試計畫, 環境, 驗證與除錯. 2. IP開發驗證. 3. 研究分析IP比較與效能評比. 4. 制定IP驗證機制與強化重複性測試環境以提供給產品使用. 5. 負責在計畫時程規劃內完成IP驗證與除錯.