交大專區

AS deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. -SHBG DV is in charge of development and implementation of TV, monitor and smart home product line verification plan. -It included: integrated simulation/verification env development, BUS fabric verification, Serdes IP verification, and architecture explore by ESL. -Need to leverage the latest EDA tool and concept to accomplish the verification plan

1. 訂定DFT plan 及執行 DFT/ATPG相關任務 2. 協助改善ATPG效率 3. 提供量產ATPG pattern 及協助量產階段除錯

專案管理 客戶夥伴關係 客戶工程技術支持 (4G/5G modem/protocol/system)

802.11無線網路協定與驅動開發

高速通訊系統的演算法與架構設計(USB/DP/HDMI/SerDes)

1. 研究IP開發測試計畫, 環境, 驗證與除錯. 2. IP開發驗證. 3. 研究分析IP比較與效能評比. 4. 制定IP驗證機制與強化重複性測試環境以提供給產品使用. 5. 負責在計畫時程規劃內完成IP驗證與除錯.

The Modem Technology Architecture team is currently involved in the architecture definition, design and validation of MediaTek’s 5G NR chipsets. In your role as Modem Architect, you will be responsible for the architecture definition of state of the art cellular modems used in User Equipment (UE) devices. You will be comfortable working across HW/SW boundaries and will have experience exploring and quantifying the impact of different architecture decisions on performance, area and power consumption.

根據不同專案使用的各種CPU架構: 1. 計畫用於system bring-up, DVT, 以及量產所需的function pattern 2. 開發function pattern(程式撰寫與模擬等等) 3. 基於對CPU design的了解以及pattern調整, debug post-silicon問題(DPPM fail or RMA等等)

1. 5G NR/Pre6G 通訊平台開發 (a) 5G gNodeB/UE 測試系統 開發 (b) L1 test mode演算法通訊平台開發 2. 5G NR通訊系統分析 (a) 5G NR實體層規格及流程驗證 (b) 基頻演算法設計驗證及訊號分析 (c) 整體系統效能驗證與流程分析 3. Modem 4/5G system level / physical layer issue analysis (a) Develop and integrate build and auto testing process (b) Collect / analyze system requirement & system design (c) Support urgent system function or performance problem

IO電路和ESD防護設計, 工作內容包含 (1) ESD/LUP防護設計 (2) IC ESD/LUP防護檢查 (3) 有EOS/Surge/System ESD 設計經驗尤佳

1. 10G/5G/2.5G Ethernet MAC/ BASET PHY開發 2. 訊號處理與通訊演算法實現 3. 系統整合與驗證

1 Develop the IR signoff criterion for leading process node and 3DIC. 2 Maintain the IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable IR violation 3 Develop new IR signoff methodology to be applied during chip synthesis/APR/STA/IR . 4 SPICE correlation for new IR signoff criterion 5 Regression test for every signoff methodology by IR results

- Develop robust 3DIC PDN considering PDN impacts - Build and analyze 3DIC IR results and propose solutions - Define area-efficient stacking possibilities, robust PG structure for different IP styles - Provide quick assessment to IR severity and improved approaches - Explore EDA tool new features and introduce to project team

In this role, you will be responsible to develop new hardware/chip architectures, technologies, designs and methodologies for Mediatek’s silicon solution to address advanced chiplet architectures in 2D, 2.5D and 3D configurations. Mediatek provides the challenging and exciting technical position where you will have the opportunities to explore and define the next generation silicon solutions. Major Responsibilities: • Develop new product and chip architectures, analyze the key metrics such as power, performance, area, scalability and reusability for chiplet • Develop new methodologies for chiplet design and mass production flow

Analog/RF IC layout

先進封裝產品Substrate( or RDL) 之佈線

In this role, you will be a member of the System-Level-Cache (SLC) design team, working with architecture, modeling, silicon, software and other design teams to develop competitive SLC design. We are looking for highly motivated, hands-on individuals who are passionate about memory performance improvement to benefit memory access behavior in sophisticated system. Major Responsibilities: •Co-work with system architect to develop competitive memory system architecture • Analyze/improve memory system performance including latency and efficiency • Responsible for micro architecture planning and RTL design coding •Integrate IP into project and meet schedule and P.P.A. requirement •Co-work with DV team to well verify RTL design •Support software team to resolve memory system related issue

類比及射頻積體電路佈局工程師

1. 高速 CPU 實作設計流程開發 2. 高速 CPU synthesis / APR

In this role, you will be a member of the System-on-Chip (SoC) Infrastructure team, responsible for Architecture and design for high-performance, low-power on chip interconnect and fabric components. Analyze the interconnect fabric at SOC level and sub-subsystem level and configure fabric components to meet bandwidth, latency, power needs of SOC. Work with cross function teams (architect, hardware, software, verification…) to develop system models and IPs for different architectural options for power, performance and cost trade offs.